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Results 1 - 7 of 7 for UMULL (0.07 sec)

  1. src/cmd/internal/obj/arm64/anames.go

    	"UBFIZW",
    	"UBFM",
    	"UBFMW",
    	"UBFX",
    	"UBFXW",
    	"UCVTFD",
    	"UCVTFS",
    	"UCVTFWD",
    	"UCVTFWS",
    	"UDIV",
    	"UDIVW",
    	"UMADDL",
    	"UMNEGL",
    	"UMSUBL",
    	"UMULH",
    	"UMULL",
    	"UREM",
    	"UREMW",
    	"UXTB",
    	"UXTBW",
    	"UXTH",
    	"UXTHW",
    	"UXTW",
    	"VADD",
    	"VADDP",
    	"VADDV",
    	"VAND",
    	"VBCAX",
    	"VBIF",
    	"VBIT",
    	"VBSL",
    	"VCMEQ",
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Thu May 18 01:40:37 UTC 2023
    - 5.4K bytes
    - Viewed (0)
  2. src/cmd/compile/internal/ssa/_gen/ARM64Ops.go

    		{name: "MULL", argLength: 2, reg: gp21, asm: "SMULL", commutative: true},                                      // arg0 * arg1, signed, 32-bit mult results in 64-bit
    		{name: "UMULL", argLength: 2, reg: gp21, asm: "UMULL", commutative: true},                                     // arg0 * arg1, unsigned, 32-bit mult results in 64-bit
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Thu May 23 15:49:20 UTC 2024
    - 58.8K bytes
    - Viewed (0)
  3. src/cmd/asm/internal/asm/testdata/arm64enc.s

    	UMADDL R0, R20, R17, R17                   // 3152a09b
    	UMSUBL R22, R4, R3, R7                     // 6790b69b
    	UMNEGL R3, R19, R1                         // 61fea39b
    	UMULH R24, R20, R24                        // 987ed89b
    	UMULL R19, R22, R19                        // d37eb39b
    	UXTBW R2, R6                               // 461c0053
    	UXTHW R7, R20                              // f43c0053
    	VCNT V0.B8, V0.B8                          // 0058200e
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Mon Jul 24 01:11:41 UTC 2023
    - 43.9K bytes
    - Viewed (0)
  4. src/cmd/compile/internal/ssa/_gen/ARM64.rules

    (Mul(32|16|8) ...) => (MULW ...)
    (Mul(32|64)F  ...) => (FMUL(S|D) ...)
    
    (Hmul64  ...) => (MULH ...)
    (Hmul64u ...) => (UMULH ...)
    (Hmul32  x y) => (SRAconst (MULL <typ.Int64> x y) [32])
    (Hmul32u x y) => (SRAconst (UMULL <typ.UInt64> x y) [32])
    (Select0 (Mul64uhilo x y)) => (UMULH x y)
    (Select1 (Mul64uhilo x y)) => (MUL x y)
    
    (Div64 [false] x y) => (DIV  x y)
    (Div32 [false] x y) => (DIVW x y)
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Thu May 23 15:49:20 UTC 2024
    - 113.1K bytes
    - Viewed (0)
  5. src/cmd/internal/obj/arm64/asm7.go

    			rel.Off = int32(c.pc)
    			rel.Siz = 4
    			rel.Sym = p.To.Sym
    			rel.Add = p.To.Offset
    			rel.Type = objabi.R_ADDR
    			o1 = 0
    		}
    
    	case 15: /* mul/mneg/umulh/umull r,[r,]r; madd/msub/fmadd/fmsub/fnmadd/fnmsub Rm,Ra,Rn,Rd */
    		o1 = c.oprrr(p, p.As)
    
    		rf := int(p.From.Reg)
    		rt := int(p.To.Reg)
    		var r int
    		var ra int
    		if p.From3Type() == obj.TYPE_REG {
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Wed May 15 15:44:14 UTC 2024
    - 201.1K bytes
    - Viewed (0)
  6. src/cmd/compile/internal/ssa/rewriteARM64.go

    	}
    }
    func rewriteValueARM64_OpHmul32u(v *Value) bool {
    	v_1 := v.Args[1]
    	v_0 := v.Args[0]
    	b := v.Block
    	typ := &b.Func.Config.Types
    	// match: (Hmul32u x y)
    	// result: (SRAconst (UMULL <typ.UInt64> x y) [32])
    	for {
    		x := v_0
    		y := v_1
    		v.reset(OpARM64SRAconst)
    		v.AuxInt = int64ToAuxInt(32)
    		v0 := b.NewValue0(v.Pos, OpARM64UMULL, typ.UInt64)
    		v0.AddArg2(x, y)
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Thu May 23 15:49:20 UTC 2024
    - 608.6K bytes
    - Viewed (0)
  7. src/cmd/compile/internal/ssa/opGen.go

    			},
    			outputs: []outputInfo{
    				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
    			},
    		},
    	},
    	{
    		name:        "UMULL",
    		argLen:      2,
    		commutative: true,
    		asm:         arm64.AUMULL,
    		reg: regInfo{
    			inputs: []inputInfo{
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Thu May 23 15:49:20 UTC 2024
    - 1M bytes
    - Viewed (0)
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