return (x << 24 >> 12) | (y & 0xfff0000000000fff)
}

// bfxil
func bfxil1(x, y uint64) uint64 {
	// arm64:"BFXIL\t[$]5, R[0-9]+, [$]12",-"LSL",-"LSR",-"AND"
	return ((x >> 5) & 0xfff) | (y & 0xfffffffffffff000)
}

func bfxil2(x, y uint64) uint64 {
	// arm64:"BFXIL\t[$]12, R[0-9]+, [$]40",-"LSL",-"LSR",-"AND"
	return (x << 12 >> 24) | (y & 0xffffff0000000000)
}

// sbfiz

	"ADRP",
	"AESD",
	"AESE",
	"AESIMC",
	"AESMC",
	"AND",
	"ANDS",
	"ANDSW",
	"ANDW",
	"ASR",
	"ASRW",
	"AT",
	"BCC",
	"BCS",
	"BEQ",
	"BFI",
	"BFIW",
	"BFM",
	"BFMW",
	"BFXIL",
	"BFXILW",
	"BGE",
	"BGT",
	"BHI",
	"BHS",
	"BIC",
	"BICS",
	"BICSW",
	"BICW",
	"BLE",
	"BLO",
	"BLS",
	"BLT",
	"BMI",
	"BNE",
	"BPL",
	"BRK",
	"BVC",
	"BVS",

Examples:

	FMADDD F30, F20, F3, F29    <=>    fmadd d29, d3, d30, d20
	FNMSUBS F7, F25, F7, F22    <=>    fnmsub s22, s7, s7, s25

(4) BFI, BFXIL, SBFIZ, SBFX, UBFIZ, UBFX $<lsb>, <Rn>, $<width>, <Rd>

Examples:

	BFIW $16, R20, $6, R0      <=>    bfi w0, w20, #16, #6
	UBFIZ $34, R26, $5, R20    <=>    ubfiz x20, x26, #34, #5

			rno := uint16(r)
			if rno <= uint16(WZR) {
				op += "W"
			}
		}
		args[1], args[2] = args[2], args[1]

	case STLXRB, STLXRH, STXRB, STXRH:
		args[1], args[2] = args[2], args[1]

	case BFI, BFXIL, SBFIZ, SBFX, UBFIZ, UBFX:
		if r, ok := inst.Args[0].(Reg); ok {
			rno := uint16(r)
			if rno <= uint16(WZR) {
				op += "W"
			}
		}
		args[1], args[2], args[3] = args[3], args[1], args[2]

		// extract width bits of arg1 starting at bit lsb and insert at low end of result, copy other bits from arg0
		{name: "BFXIL", argLength: 2, reg: gp21nog, asm: "BFXIL", aux: "ARM64BitField", resultInArg0: true},

	=> (BFI [armBFAuxInt(lc-rc, 64-lc)] x y)
// bfxil
(OR (UBFX [bfc] x) (ANDconst [ac] y)) && ac == ^(1<<uint(bfc.getARM64BFwidth())-1)
	=> (BFXIL [bfc] y x)
(ORshiftLL [sc] (UBFX [bfc] x) (SRLconst [sc] y)) && sc == bfc.getARM64BFwidth()
	=> (BFXIL [bfc] y x)
(ORshiftRL [rc] (ANDconst [ac] y) (SLLconst [lc] x)) && lc < rc && ac == ^((1<<uint(64-rc)-1))
	=> (BFXIL [armBFAuxInt(rc-lc, 64-rc)] y x)

// FP simplification

	JMP -1(PC)                                 // ffffff17
	BFIW $16, R20, $6, R0                      // 80161033
	BFI $27, R21, $21, R25                     // b95265b3
	BFXILW $3, R27, $23, R14                   // 6e670333
	BFXIL $26, R8, $16, R20                    // 14a55ab3
	BICW R7@>15, R5, R16                       // b03ce70a
	BIC R12@>13, R12, R19                      // 9335ec8a
	BICSW R25->20, R3, R20                     // 7450b96a

			v.AddArg2(y, x)
			return true
		}
		break
	}
	// match: (OR (UBFX [bfc] x) (ANDconst [ac] y))
	// cond: ac == ^(1<<uint(bfc.getARM64BFwidth())-1)
	// result: (BFXIL [bfc] y x)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			if v_0.Op != OpARM64UBFX {
				continue
			}
			bfc := auxIntToArm64BitField(v_0.AuxInt)
			x := v_0.Args[0]

			},
			outputs: []outputInfo{
				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
		},
	},
	{
		name:         "BFXIL",
		auxType:      auxARM64BitField,
		argLen:       2,
		resultInArg0: true,
		asm:          arm64.ABFXIL,
		reg: regInfo{
			inputs: []inputInfo{