MULSD   X5, X5 // x1= k, x2= f, x3= s, x4= s2, x5= s4
	// t1 := s2 * (L1 + s4*(L3+s4*(L5+s4*L7)))
	MOVSD   $L7, X6
	MULSD   X5, X6
	ADDSD   $L5, X6
	MULSD   X5, X6
	ADDSD   $L3, X6
	MULSD   X5, X6
	ADDSD   $L1, X6
	MULSD   X6, X4 // x1= k, x2= f, x3= s, x4= t1, x5= s4
	// t2 := s4 * (L2 + s4*(L4+s4*L6))
	MOVSD   $L6, X6
	MULSD   X5, X6
	ADDSD   $L4, X6
	MULSD   X5, X6
	ADDSD   $L2, X6

// --------------------- //

func Mul2(f float64) float64 {
	// 386/sse2:"ADDSD",-"MULSD"
	// amd64:"ADDSD",-"MULSD"
	// arm/7:"ADDD",-"MULD"
	// arm64:"FADDD",-"FMULD"
	// ppc64x:"FADD",-"FMUL"
	// riscv64:"FADDD",-"FMULD"
	return f * 2.0
}

func DivPow2(f1, f2, f3 float64) (float64, float64, float64) {
	// 386/sse2:"MULSD",-"DIVSD"
	// amd64:"MULSD",-"DIVSD"
	// arm/7:"MULD",-"DIVD"
	// arm64:"FMULD",-"FDIVD"

	// See issue 36400.
	zero := 0.0
	// amd64:-"DIVSD"
	inf := 1 / zero // +inf. We can constant propagate this one.
	negone := -1.0

	// amd64:"DIVSD"
	z0 := zero / zero
	// amd64:"MULSD"
	z1 := zero * inf
	// amd64:"SQRTSD"
	z2 := math.Sqrt(negone)
	return z0 + z1 + z2
}

func nanGenerate32() float32 {
	zero := float32(0.0)
	// amd64:-"DIVSS"

	"MOVSWW",
	"MOVUPD",
	"MOVUPS",
	"MOVW",
	"MOVWLSX",
	"MOVWLZX",
	"MOVWQSX",
	"MOVWQZX",
	"MOVZWW",
	"MPSADBW",
	"MULB",
	"MULL",
	"MULPD",
	"MULPS",
	"MULQ",
	"MULSD",
	"MULSS",
	"MULW",
	"MULXL",
	"MULXQ",
	"MWAIT",
	"NEGB",
	"NEGL",
	"NEGQ",
	"NEGW",
	"NOPL",
	"NOPW",
	"NOTB",
	"NOTL",
	"NOTQ",
	"NOTW",
	"ORB",
	"ORL",

		{name: "MULSS", argLength: 2, reg: fp21, asm: "MULSS", commutative: true, resultInArg0: true}, // fp32 mul
		{name: "MULSD", argLength: 2, reg: fp21, asm: "MULSD", commutative: true, resultInArg0: true}, // fp64 mul
		{name: "DIVSS", argLength: 2, reg: fp21, asm: "DIVSS", resultInArg0: true},                    // fp32 div

	{VMLA_EQ_F32, []int{2, 1, 0}, "VMLA", "MULAF"},
	{VMLA_EQ_F64, []int{2, 1, 0}, "VMLA", "MULAD"},
	{VMLS_EQ_F32, []int{2, 1, 0}, "VMLS", "MULSF"},
	{VMLS_EQ_F64, []int{2, 1, 0}, "VMLS", "MULSD"},
	{VNMLA_EQ_F32, []int{2, 1, 0}, "VNMLA", "NMULAF"},
	{VNMLA_EQ_F64, []int{2, 1, 0}, "VNMLA", "NMULAD"},
	{VNMLS_EQ_F32, []int{2, 1, 0}, "VNMLS", "NMULSF"},
	{VNMLS_EQ_F64, []int{2, 1, 0}, "VNMLS", "NMULSD"},

		{name: "SUBSD", argLength: 2, reg: fp21, asm: "SUBSD", resultInArg0: true},
		{name: "MULSS", argLength: 2, reg: fp21, asm: "MULSS", commutative: true, resultInArg0: true},
		{name: "MULSD", argLength: 2, reg: fp21, asm: "MULSD", commutative: true, resultInArg0: true},
		{name: "DIVSS", argLength: 2, reg: fp21, asm: "DIVSS", resultInArg0: true},
		{name: "DIVSD", argLength: 2, reg: fp21, asm: "DIVSD", resultInArg0: true},

		{name: "MULAD", argLength: 3, reg: fp31, asm: "MULAD", resultInArg0: true}, // arg0 + (arg1 * arg2)
		{name: "MULSF", argLength: 3, reg: fp31, asm: "MULSF", resultInArg0: true}, // arg0 - (arg1 * arg2)
		{name: "MULSD", argLength: 3, reg: fp31, asm: "MULSD", resultInArg0: true}, // arg0 - (arg1 * arg2)

		// FMULAD only exists on platforms with the VFPv4 instruction set.
		// Any use must be preceded by a successful check of runtime.arm_support_vfpv4.

	c := float64(7)
	// amd64: `ADDSD\t8\([A-Z]+[0-9]*\)\([A-Z]+[0-9]*\*8\), X[0-9]+`
	c += a[i+1]
	// amd64: `SUBSD\t16\([A-Z]+[0-9]*\)\([A-Z]+[0-9]*\*8\), X[0-9]+`
	c -= a[i+2]
	// amd64: `MULSD\t24\([A-Z]+[0-9]*\)\([A-Z]+[0-9]*\*8\), X[0-9]+`
	c *= a[i+3]
	// amd64: `DIVSD\t32\([A-Z]+[0-9]*\)\([A-Z]+[0-9]*\*8\), X[0-9]+`
	c /= a[i+4]

	d := float32(8)

(ADDD a (NMULD x y)) && a.Uses == 1 && buildcfg.GOARM.Version >= 6 => (MULSD a x y)
(SUBF a (MULF x y)) && a.Uses == 1 && buildcfg.GOARM.Version >= 6 => (MULSF a x y)
(SUBF a (NMULF x y)) && a.Uses == 1 && buildcfg.GOARM.Version >= 6 => (MULAF a x y)
(SUBD a (MULD x y)) && a.Uses == 1 && buildcfg.GOARM.Version >= 6 => (MULSD a x y)
(SUBD a (NMULD x y)) && a.Uses == 1 && buildcfg.GOARM.Version >= 6 => (MULAD a x y)