=> (UBFX [armBFAuxInt(sc, arm64BFWidth(ac, sc))] x)
// merge ANDconst and ubfx into ubfx
(ANDconst [c] (UBFX [bfc] x)) && isARM64BFMask(0, c, 0) =>
	(UBFX [armBFAuxInt(bfc.getARM64BFlsb(), min(bfc.getARM64BFwidth(), arm64BFWidth(c, 0)))] x)
(UBFX [bfc] (ANDconst [c] x)) && isARM64BFMask(0, c, 0) && bfc.getARM64BFlsb() + bfc.getARM64BFwidth() <= arm64BFWidth(c, 0) =>
	(UBFX [bfc] x)
// merge ubfx and zerso-extension into ubfx

Examples:

	FMADDD F30, F20, F3, F29    <=>    fmadd d29, d3, d30, d20
	FNMSUBS F7, F25, F7, F22    <=>    fnmsub s22, s7, s7, s25

(4) BFI, BFXIL, SBFIZ, SBFX, UBFIZ, UBFX $<lsb>, <Rn>, $<width>, <Rd>

Examples:

	BFIW $16, R20, $6, R0      <=>    bfi w0, w20, #16, #6
	UBFIZ $34, R26, $5, R20    <=>    ubfiz x20, x26, #34, #5

			break
		}
		v.reset(OpARM64UBFX)
		v.AuxInt = arm64BitFieldToAuxInt(armBFAuxInt(sc, arm64BFWidth(ac, 0)))
		v.AddArg(x)
		return true
	}
	// match: (ANDconst [c] (UBFX [bfc] x))
	// cond: isARM64BFMask(0, c, 0)
	// result: (UBFX [armBFAuxInt(bfc.getARM64BFlsb(), min(bfc.getARM64BFwidth(), arm64BFWidth(c, 0)))] x)
	for {
		c := auxIntToInt64(v.AuxInt)
		if v_0.Op != OpARM64UBFX {
			break
		}

	// s390x:-"MOVW",-"SRD"
	p.b = uint32(x)
}
func store16le(p *struct{ a, b uint16 }, x uint32) {
	// amd64:"MOVL",-"MOVW",-"SHRL"
	// arm64:"MOVW",-"MOVH",-"UBFX"
	// ppc64le:"MOVW",-"MOVH",-"SRW"
	p.a = uint16(x)
	// amd64:-"MOVW",-"SHRL"
	// arm64:-"MOVH",-"UBFX"
	// ppc64le:-"MOVH",-"SRW"
	p.b = uint16(x >> 16)
}
func store16be(p *struct{ a, b uint16 }, x uint32) {
	// ppc64:"MOVW",-"MOVH",-"SRW"

	// 386:"BSWAPL"
	// s390x:"MOVWBR"
	// arm64:"REVW"
	// ppc64x/power10: "BRW"
	return bits.ReverseBytes32(n)
}

func ReverseBytes16(n uint16) uint16 {
	// amd64:"ROLW"
	// arm64:"REV16W",-"UBFX",-"ORR"
	// arm/5:"SLL","SRL","ORR"
	// arm/6:"REV16"
	// arm/7:"REV16"
	// ppc64x/power10: "BRH"
	return bits.ReverseBytes16(n)
}

// --------------------- //
//    bits.RotateLeft    //

		{name: "UBFIZ", argLength: 1, reg: gp11, asm: "UBFIZ", aux: "ARM64BitField"},
		// extract width bits of arg0 starting at bit lsb and insert at low end of result, remaining high bits are zeroed
		{name: "UBFX", argLength: 1, reg: gp11, asm: "UBFX", aux: "ARM64BitField"},

		// moves
		{name: "MOVDconst", argLength: 0, reg: gp01, aux: "Int64", asm: "MOVD", typ: "UInt64", rematerializeable: true},      // 64 bits from auxint

	ANDS R17<<11, R24, ZR                      // 1f2f11ea
	UBFIZW $3, R19, $14, R14                   // 6e361d53
	UBFIZ $3, R22, $14, R4                     // c4367dd3
	UBFXW $3, R7, $20, R15                     // ef580353
	UBFX $33, R17, $25, R5                     // 25e661d3
	UDIVW R8, R21, R15                         // af0ac81a
	UDIV R2, R19, R21                          // 750ac29a
	UMADDL R0, R20, R17, R17                   // 3152a09b

(RotateLeft32 x y) => (SRR x (RSBconst [0] <y.Type> y))

// ((x>>8) | (x<<8)) -> (REV16 x), the type of x is uint16, "|" can also be "^" or "+".
// UBFX instruction is supported by ARMv6T2, ARMv7 and above versions, REV16 is supported by
// ARMv6 and above versions. So for ARMv6, we need to match SLLconst, SRLconst and ORshiftLL.

			},
			outputs: []outputInfo{
				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
		},
	},
	{
		name:    "UBFX",
		auxType: auxARM64BitField,
		argLen:  1,
		asm:     arm64.AUBFX,
		reg: regInfo{
			inputs: []inputInfo{