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Results 1 - 10 of 13 for SLLV (0.04 sec)
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src/internal/runtime/atomic/atomic_loong64.s
MOVBU val+8(FP), R5 // Align ptr down to 4 bytes so we can use 32-bit load/store. MOVV $~3, R6 AND R4, R6 // R7 = ((ptr & 3) * 8) AND $3, R4, R7 SLLV $3, R7 // Shift val for aligned ptr. R5 = val << R7 | ^(0xFF << R7) MOVV $0xFF, R8 SLLV R7, R5 SLLV R7, R8 NOR R0, R8 OR R8, R5 DBAR LL (R6), R7 AND R5, R7 SC R7, (R6) BEQ R7, -4(PC) DBAR RET
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon Mar 25 19:53:03 UTC 2024 - 6.3K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/MIPS64.rules
(Lsh64x32 <t> x y) => (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) (ZeroExt32to64 y))) (SLLV <t> x (ZeroExt32to64 y))) (Lsh64x16 <t> x y) => (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) (ZeroExt16to64 y))) (SLLV <t> x (ZeroExt16to64 y))) (Lsh64x8 <t> x y) => (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) (ZeroExt8to64 y))) (SLLV <t> x (ZeroExt8to64 y)))
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon Jul 31 03:59:48 UTC 2023 - 41.9K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/LOONG64.rules
(Lsh64x64 <t> x y) => (MASKEQZ (SLLV <t> x y) (SGTU (MOVVconst <typ.UInt64> [64]) y)) (Lsh64x32 <t> x y) => (MASKEQZ (SLLV <t> x (ZeroExt32to64 y)) (SGTU (MOVVconst <typ.UInt64> [64]) (ZeroExt32to64 y))) (Lsh64x16 <t> x y) => (MASKEQZ (SLLV <t> x (ZeroExt16to64 y)) (SGTU (MOVVconst <typ.UInt64> [64]) (ZeroExt16to64 y)))
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Nov 21 19:26:25 UTC 2023 - 31.8K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/loong64enc1.s
SLL R4, R5, R6 // a6101700 SRL R4, R5 // a5901700 SRL R4, R5, R6 // a6901700 SRA R4, R5 // a5101800 SRA R4, R5, R6 // a6101800 ROTR R4, R5 // a5101b00 ROTR R4, R5, R6 // a6101b00 SLLV R4, R5 // a5901800 SLLV R4, R5, R6 // a6901800 ROTRV R4, R5 // a5901b00 ROTRV R4, R5, R6 // a6901b00 CLO R4, R5 // 85100000 CLZ R4, R5 // 85140000 ADDF F4, F5 // a5900001 ADDF F4, R5, F6 // a6900001
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed May 22 02:04:54 UTC 2024 - 8.2K bytes - Viewed (0) -
src/internal/runtime/atomic/atomic_mips64x.s
// Compute val shift. #ifdef GOARCH_mips64 // Big endian. ptr = ptr ^ 3 XOR $3, R1 #endif // R4 = ((ptr & 3) * 8) AND $3, R1, R4 SLLV $3, R4 // Shift val for aligned ptr. R2 = val << R4 | ^(0xFF << R4) MOVV $0xFF, R5 SLLV R4, R2 SLLV R4, R5 NOR R0, R5 OR R5, R2 SYNC LL (R3), R4 AND R2, R4 SC R4, (R3) BEQ R4, -4(PC) SYNC RET
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Sat May 11 21:29:34 UTC 2024 - 7.2K bytes - Viewed (0) -
src/cmd/internal/obj/mips/anames.go
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Aug 08 12:17:12 UTC 2023 - 1.4K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/mips64.s
// } SLL R1, R2, R3 // 00221804 SLLV R10, R22, R21 // 0156a814 SRL R27, R6, R17 // 03668806 SRLV R27, R6, R17 // 03668816 SRA R11, R19, R20 // 0173a007 SRAV R20, R19, R19 // 02939817 ROTR R19, R18, R20 // 0272a046 ROTRV R9, R13, R16 // 012d8056 // LSHW rreg ',' rreg // { // outcode(int($1), &$2, 0, &$4); // } SLL R1, R2 // 00221004 SLLV R10, R22 // 0156b014 SRL R27, R6 // 03663006
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Aug 08 12:17:12 UTC 2023 - 12.4K bytes - Viewed (0) -
src/cmd/internal/obj/loong64/anames.go
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed May 22 02:04:54 UTC 2024 - 1.9K bytes - Viewed (0) -
src/runtime/cgo/asm_mips64x.s
MOVD F29, (8*20)(R29) MOVD F30, (8*21)(R29) MOVD F31, (8*22)(R29) #endif // Initialize Go ABI environment // prepare SB register = PC & 0xffffffff00000000 BGEZAL R0, 1(PC) SRLV $32, R31, RSB SLLV $32, RSB JAL runtimeĀ·load_g(SB) JAL runtimeĀ·cgocallback(SB) MOVV (8*4)(R29), R16 MOVV (8*5)(R29), R17 MOVV (8*6)(R29), R18 MOVV (8*7)(R29), R19 MOVV (8*8)(R29), R20 MOVV (8*9)(R29), R21
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu Oct 12 00:43:51 UTC 2023 - 2.5K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/LOONG64Ops.go
{name: "MASKNEZ", argLength: 2, reg: gp21, asm: "MASKNEZ"}, // returns 0 if arg1 != 0, otherwise returns arg0 // shifts {name: "SLLV", argLength: 2, reg: gp21, asm: "SLLV"}, // arg0 << arg1, shift amount is mod 64 {name: "SLLVconst", argLength: 1, reg: gp11, asm: "SLLV", aux: "Int64"}, // arg0 << auxInt
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Nov 21 19:04:19 UTC 2023 - 25.2K bytes - Viewed (0)