X128,
    X129,
    X130,
    X131,
    X132,
    X133,
    X134,
    X135,
    X136,
    X137,
    X138,
    X139,
    X140,
    X141,
    X142,
    X143,
    X144,
    X145,
    X146,
    X147,
    X148,
    X149,
    X150,
    X151,
    X152,
    X153,
    X154,
    X155,
    X156,
    X157,
    X158,
    X159,

	VPDPWSSDS 17(SP)(BP*8), X15, K2, X30               // 6262050a53b4ec11000000
	VPDPWSSDS 17(SP)(BP*4), X15, K2, X30               // 6262050a53b4ac11000000
	VPDPWSSDS X13, X30, K2, X30                        // 62420d0253f5
	VPDPWSSDS X6, X30, K2, X30                         // 62620d0253f6
	VPDPWSSDS X12, X30, K2, X30                        // 62420d0253f4
	VPDPWSSDS 17(SP)(BP*8), X30, K2, X30               // 62620d0253b4ec11000000

	VPERMB X0, X2, K1, X30                             // 62626d098df0
	VPERMB 7(SI)(DI*4), X2, K1, X30                    // 62626d098db4be07000000
	VPERMB -7(DI)(R8*2), X2, K1, X30                   // 62226d098db447f9ffffff
	VPERMB X26, X9, K1, X30                            // 620235098df2
	VPERMB X19, X9, K1, X30                            // 622235098df3

	VAESENC X14, X16, X13                              // 62527d00dcee or 6252fd00dcee
	VAESENC X19, X16, X13                              // 62327d00dceb or 6232fd00dceb
	VAESENC X8, X16, X13                               // 62527d00dce8 or 6252fd00dce8
	VAESENC 99(R15)(R15*8), X16, X13                   // 62127d00dcacff63000000 or 6212fd00dcacff63000000

	VLSE8V		(X10), X10, X11			// ERROR "expected vector register in vd position"
	VLSE8V		(V1), X10, V3			// ERROR "expected integer register in rs1 position"
	VLSE8V		(X10), V1, V0, V3		// ERROR "expected integer register in rs2 position"
	VSSE8V		V3, (X10)			// ERROR "expected integer register in rs2 position"
	VSSE8V		X10, X11, (X10)			// ERROR "expected vector register in vd position"
	VSSE8V		V3, X11, (V1)			// ERROR "expected integer register in rs1 position"

	VPSHUFBITQMB X24, X13, K6, K0                      // 6292150e8fc0
	VPSHUFBITQMB X7, X13, K6, K0                       // 62f2150e8fc7
	VPSHUFBITQMB X0, X13, K6, K0                       // 62f2150e8fc0
	VPSHUFBITQMB (R8), X13, K6, K0                     // 62d2150e8f00
	VPSHUFBITQMB 15(DX)(BX*2), X13, K6, K0             // 62f2150e8f845a0f000000

	{"R13", "R13"},
	{"R14", "R14"},
	{"R15", "R15"},
	{"R8", "R8"},
	{"R9", "R9"},
	{"g", "R14"},
	{"SI", "SI"},
	{"SP", "SP"},
	{"X0", "X0"},
	{"X1", "X1"},
	{"X10", "X10"},
	{"X11", "X11"},
	{"X12", "X12"},
	{"X13", "X13"},
	{"X14", "X14"},
	{"X15", "X15"},
	{"X2", "X2"},
	{"X3", "X3"},
	{"X4", "X4"},
	{"X5", "X5"},
	{"X6", "X6"},
	{"X7", "X7"},
	{"X8", "X8"},
	{"X9", "X9"},

	VPLZCNTQ X9, K2, X13                               // 6252fd0a44e9
	VPLZCNTQ X15, K2, X13                              // 6252fd0a44ef
	VPLZCNTQ X26, K2, X13                              // 6212fd0a44ea
	VPLZCNTQ -17(BP), K2, X13                          // 6272fd0a44adefffffff
	VPLZCNTQ -15(R14)(R15*8), K2, X13                  // 6212fd0a44acfef1ffffff

            assertEquals("Invalid format: 12:60", e.getMessage());
        }

        try {
            IntervalControlHelper.parseTime("-1:30");
            fail("Should throw FessSystemException");
        } catch (FessSystemException e) {
            assertEquals("Invalid format: -1:30", e.getMessage());
        }
    }

    public void test_intervalRule_getDelay() {

    // Now we hit the cap
    assertEquals(1 << 30, ImmutableSet.chooseTableSize(1 << 29));
    assertEquals(1 << 30, ImmutableSet.chooseTableSize((1 << 30) - 1));

    // Now we've gone too far
    assertThrows(IllegalArgumentException.class, () -> ImmutableSet.chooseTableSize(1 << 30));
  }

  @GwtIncompatible // RegularImmutableSet.table not in emulation