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Results 1 - 10 of 10 for f0 (0.03 sec)

  1. src/cmd/asm/internal/asm/testdata/armerror.s

    	NMULSD	F0, F1             // ERROR "illegal combination"
    	NMULSF	F0, F1             // ERROR "illegal combination"
    	FMULAD	F0, F1             // ERROR "illegal combination"
    	FMULAF	F0, F1             // ERROR "illegal combination"
    	FMULSD	F0, F1             // ERROR "illegal combination"
    	FMULSF	F0, F1             // ERROR "illegal combination"
    	FNMULAD	F0, F1             // ERROR "illegal combination"
    Registered: Tue Nov 05 11:13:11 UTC 2024
    - Last Modified: Wed Oct 23 15:18:14 UTC 2024
    - 14.5K bytes
    - Viewed (0)
  2. src/cmd/asm/internal/asm/testdata/riscv64.s

    	FCVTLS.RUP	F0, X5				// d33220c0
    	FCVTLS.RMM	F0, X5				// d34220c0
    	FCVTSW	X5, F0					// 538002d0
    	FCVTSL	X5, F0					// 538022d0
    	FCVTWUS	F0, X5					// d31210c0
    	FCVTWUS.RNE	F0, X5				// d30210c0
    	FCVTWUS.RTZ	F0, X5				// d31210c0
    	FCVTWUS.RDN	F0, X5				// d32210c0
    	FCVTWUS.RUP	F0, X5				// d33210c0
    	FCVTWUS.RMM	F0, X5				// d34210c0
    	FCVTLUS	F0, X5					// d31230c0
    	FCVTLUS.RNE	F0, X5				// d30230c0
    Registered: Tue Nov 05 11:13:11 UTC 2024
    - Last Modified: Fri Oct 25 12:05:29 UTC 2024
    - 16.8K bytes
    - Viewed (0)
  3. src/cmd/asm/internal/asm/testdata/loong64enc1.s

    	FCLASSD		F4, F5		// 85381401
    
    	FFINTFW		F0, F1		// 01101d01
    	FFINTFV		F0, F1		// 01181d01
    	FFINTDW		F0, F1		// 01201d01
    	FFINTDV		F0, F1		// 01281d01
    	FTINTWF		F0, F1		// 01041b01
    	FTINTWD		F0, F1		// 01081b01
    	FTINTVF		F0, F1		// 01241b01
    	FTINTVD		F0, F1		// 01281b01
    
    	FTINTRMWF	F0, F2		// 02041a01
    	FTINTRMWD	F0, F2		// 02081a01
    	FTINTRMVF	F0, F2		// 02241a01
    	FTINTRMVD	F0, F2		// 02281a01
    Registered: Tue Nov 05 11:13:11 UTC 2024
    - Last Modified: Sat Nov 02 01:36:19 UTC 2024
    - 11.6K bytes
    - Viewed (0)
  4. src/cmd/asm/internal/asm/testdata/s390x.s

    	FMOVS	4095(R2)(R3), F13      // 78d32fff
    	FMOVS	4096(R2)(R4), F15      // edf420000164
    	FMOVD	F0, 4095(R1)           // 60001fff
    	FMOVD	F0, 4096(R1)           // ed0010000167
    	FMOVS	F13, 4095(R2)(R3)      // 70d32fff
    	FMOVS	F13, 4096(R2)(R3)      // edd320000166
    
    	FADDS	F0, F15                // b30a00f0
    	FADD	F1, F14                // b31a00e1
    	FSUBS	F2, F13                // b30b00d2
    Registered: Tue Nov 05 11:13:11 UTC 2024
    - Last Modified: Wed Sep 18 15:49:24 UTC 2024
    - 22.1K bytes
    - Viewed (0)
  5. src/cmd/asm/internal/asm/testdata/arm64enc.s

    	YIELD                                      // 3f2003d5
    	//TODO FABD F0, F5, F11                    // abd4a07e
    	//TODO VFABD V30.S2, V8.S2, V24.S2         // 18d5be2e
    	//TODO VFABS V5.S4, V24.S4                 // b8f8a04e
    	FABSS F2, F28                              // 5cc0201e
    	FABSD F0, F14                              // 0ec0601e
    	//TODO FACGE F25, F16, F0                  // 00ee797e
    	//TODO VFACGE V11.S2, V15.S2, V9.S2        // e9ed2b2e
    Registered: Tue Nov 05 11:13:11 UTC 2024
    - Last Modified: Mon Jul 24 01:11:41 UTC 2023
    - 43.9K bytes
    - Viewed (0)
  6. src/archive/zip/zip_test.go

    		t.Fatal(err)
    	}
    
    	// read back zip file and check that we get to the end of it
    	r, err := NewReader(buf, buf.Size())
    	if err != nil {
    		t.Fatal("reader:", err)
    	}
    	f0 := r.File[0]
    	rc, err := f0.Open()
    	if err != nil {
    		t.Fatal("opening:", err)
    	}
    	rc.(*checksumReader).hash = fakeHash32{}
    	for i := 0; i < chunks; i++ {
    		_, err := io.ReadFull(rc, chunk)
    		if err != nil {
    Registered: Tue Nov 05 11:13:11 UTC 2024
    - Last Modified: Thu May 23 01:00:11 UTC 2024
    - 19.6K bytes
    - Viewed (0)
  7. src/cmd/asm/internal/asm/operand_test.go

    	{"0(AX)", "(AX)"},
    	{"0(BP)", "(BP)"},
    	{"0(BX)", "(BX)"},
    	{"4(AX)", "4(AX)"},
    	{"AL", "AL"},
    	{"AX", "AX"},
    	{"BP", "BP"},
    	{"BX", "BX"},
    	{"CX", "CX"},
    	{"DI", "DI"},
    	{"DX", "DX"},
    	{"F0", "F0"},
    	{"GS", "GS"},
    	{"SI", "SI"},
    	{"SP", "SP"},
    	{"X0", "X0"},
    	{"X1", "X1"},
    	{"X2", "X2"},
    	{"X3", "X3"},
    	{"X4", "X4"},
    	{"X5", "X5"},
    	{"X6", "X6"},
    	{"X7", "X7"},
    Registered: Tue Nov 05 11:13:11 UTC 2024
    - Last Modified: Tue Aug 29 18:31:05 UTC 2023
    - 23.9K bytes
    - Viewed (0)
  8. src/cmd/asm/internal/asm/testdata/arm64error.s

    	FSTPD	(R1, R2), (R0)                                   // ERROR "invalid register pair"
    	FMOVS	(F2), F0                                         // ERROR "illegal combination"
    	FMOVD	F0, (F1)                                         // ERROR "illegal combination"
    	LDADDAD	R5, (R6), RSP                                    // ERROR "illegal combination"
    Registered: Tue Nov 05 11:13:11 UTC 2024
    - Last Modified: Fri Dec 08 03:28:17 UTC 2023
    - 37.8K bytes
    - Viewed (0)
  9. okhttp/src/test/resources/web-platform-test-urltestdata.txt

    # Broken IPv6
    http://[google.com]
    
    # Misc Unicode
    http://foo:\uD83D\******@****.***/bar  s:http h:example.com p:/bar u:foo pass:%F0%9F%92%A9
    
    # resolving a relative reference against an unknown scheme results in an error
    Registered: Fri Nov 01 11:42:11 UTC 2024
    - Last Modified: Wed Dec 20 23:27:07 UTC 2023
    - 14.3K bytes
    - Viewed (0)
  10. doc/asm.html

    </li>
    
    </ul>
    
    <h3 id="mips">MIPS, MIPS64</h3>
    
    <p>
    General purpose registers are named <code>R0</code> through <code>R31</code>,
    floating point registers are <code>F0</code> through <code>F31</code>.
    </p>
    
    <p>
    <code>R30</code> is reserved to point to <code>g</code>.
    <code>R23</code> is used as a temporary register.
    </p>
    
    <p>
    Registered: Tue Nov 05 11:13:11 UTC 2024
    - Last Modified: Tue Nov 28 19:15:27 UTC 2023
    - 36.3K bytes
    - Viewed (0)
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