VPMADD52LUQ X5, X9, K1, X24                        // 6262b509b4c5
	VPMADD52LUQ X31, X9, K1, X24                       // 6202b509b4c7
	VPMADD52LUQ X3, X9, K1, X24                        // 6262b509b4c3
	VPMADD52LUQ 15(R8), X9, K1, X24                    // 6242b509b4800f000000
	VPMADD52LUQ (BP), X9, K1, X24                      // 6262b509b44500
	VPMADD52LUQ X5, X7, K1, X24                        // 6262c509b4c5

	VPERMT2B X9, X9, K7, X5                            // 62d2350f7de9
	VPERMT2B (BX), X9, K7, X5                          // 62f2350f7d2b
	VPERMT2B -17(BP)(SI*1), X9, K7, X5                 // 62f2350f7dac35efffffff
	VPERMT2B X2, X13, K7, X5                           // 62f2150f7dea
	VPERMT2B X8, X13, K7, X5                           // 62d2150f7de8

	RORI	$-1, X5, X6			// ERROR "immediate out of range 0 to 63"
	SLLI	$-1, X5, X6			// ERROR "immediate out of range 0 to 63"
	SRLI	$-1, X5, X6			// ERROR "immediate out of range 0 to 63"
	SRAI	$-1, X5, X6			// ERROR "immediate out of range 0 to 63"
	RORIW	$32, X5, X6			// ERROR "immediate out of range 0 to 31"
	SLLIW	$32, X5, X6			// ERROR "immediate out of range 0 to 31"
	SRLIW	$32, X5, X6			// ERROR "immediate out of range 0 to 31"

	VPOPCNTW X5, K3, X11                               // 6272fd0b54dd
	VPOPCNTW X25, K3, X11                              // 6212fd0b54d9
	VPOPCNTW (CX), K3, X11                             // 6272fd0b5419
	VPOPCNTW 99(R15), K3, X11                          // 6252fd0b549f63000000
	VPOPCNTW X20, K3, X23                              // 62a2fd0b54fc
	VPOPCNTW X5, K3, X23                               // 62e2fd0b54fd

	{"X0", "X0"},
	{"X1", "X1"},
	{"X10", "X10"},
	{"X11", "X11"},
	{"X12", "X12"},
	{"X13", "X13"},
	{"X14", "X14"},
	{"X15", "X15"},
	{"X2", "X2"},
	{"X3", "X3"},
	{"X4", "X4"},
	{"X5", "X5"},
	{"X6", "X6"},
	{"X7", "X7"},
	{"X8", "X8"},
	{"X9", "X9"},
	{"_expand_key_128<>(SB)", "_expand_key_128<>(SB)"},
	{"_seek<>(SB)", "_seek<>(SB)"},
	{"a2+16(FP)", "a2+16(FP)"},

	VAESDEC 99(R15)(R15*1), Z12, Z25                   // 62021d48de8c3f63000000 or 62029d48de8c3f63000000
	VAESDEC (DX), Z12, Z25                             // 62621d48de0a or 62629d48de0a
	VAESDECLAST X21, X5, X9                            // 62325508dfcd or 6232d508dfcd
	VAESDECLAST X21, X31, X9                           // 62320500dfcd or 62328500dfcd
	VAESDECLAST X1, X31, X9                            // 62720500dfc9 or 62728500dfc9

// the validate function from being run and TestRISCVValidation will report missing
// errors.

TEXT validation(SB),$0
	SRLI	$1, X5, F1			// ERROR "expected integer register in rd position but got non-integer register F1"
	SRLI	$1, F1, X5			// ERROR "expected integer register in rs1 position but got non-integer register F1"

	//
	// "V" Standard Extension for Vector Operations, Version 1.0
	//

    }
    return retVal;
  }

  private enum SmallEnum {
    X0,
    X1,
    X2
  }

  private enum MediumEnum {
    X0,
    X1,
    X2,
    X3,
    X4,
    X5,
    X6,
    X7,
    X8,
    X9,
    X10,
    X11,
    X12,
    X13,
    X14,
    X15,
    X16,
    X17,
    X18,
    X19,
    X20,
    X21,
    X22,
    X23,

			x2 := int64(p.getRegister(prog, op, &a[2]))
			x3 := int64(p.getRegister(prog, op, &a[3]))
			x4 := int64(p.getRegister(prog, op, &a[4]))
			x5 := p.getConstant(prog, op, &a[5])
			// Cond is handled specially for this instruction.
			offset, MRC, ok := arch.ARMMRCOffset(op, cond, x0, x1, x2, x3, x4, x5)
			if !ok {
				p.errorf("unrecognized condition code .%q", cond)
			}
			prog.To.Offset = offset
			cond = ""

	XVMOVQ		X3, 3(R4)       // 830cc02c
	XVMOVQ		X4, 2040(R4)    // 84e0df2c
	XVMOVQ		X5, -2040(R4)   // 8520e02c
	XVMOVQ		X6, y+16(FP)    // 0660c02c
	XVMOVQ		X7, x+2030(FP)  // 07d8df2c
	XVMOVQ		(R4), X2        // 8200802c
	XVMOVQ		3(R4), X3       // 830c802c
	XVMOVQ		2044(R4), X4    // 84f09f2c
	XVMOVQ		-2044(R4), X5   // 8510a02c
	XVMOVQ		y+16(FP), X6    // 0660802c
	XVMOVQ		x+2030(FP), X7  // 07d89f2c