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Results 1 - 10 of 10 for paddi (0.2 sec)
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src/cmd/compile/internal/ssa/_gen/PPC64latelower.rules
(AND <t> x:(MOVDconst [m]) n) && t.Size() == 4 && isPPC64WordRotateMask(m) => (RLWINM [encodePPC64RotateMask(0,m,32)] n) // When PCRel is supported, paddi can add a 34b signed constant in one instruction. (ADD (MOVDconst [m]) x) && supportsPPC64PCRel() && (m<<30)>>30 == m => (ADDconst [m] x)
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed May 22 19:59:38 UTC 2024 - 3.8K bytes - Viewed (0) -
src/internal/chacha8rand/chacha8_amd64.s
REPLREG(SI, X1) REPLREG(R8, X2) REPLREG(R9, X3) REPLREG(R10, X12) REPLREG(R11, X13) REPLREG(R12, X14) REPLREG(R13, X15) PADDD X0, X4 PADDD X1, X5 PADDD X2, X6 PADDD X3, X7 PADDD X12, X8 PADDD X13, X9 PADDD X14, X10 PADDD X15, X11 MOVOU X4, (4*16)(BX) MOVOU X5, (5*16)(BX) MOVOU X6, (6*16)(BX) MOVOU X7, (7*16)(BX) MOVOU X8, (8*16)(BX) MOVOU X9, (9*16)(BX)
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Dec 05 20:34:30 UTC 2023 - 4.6K bytes - Viewed (0) -
src/runtime/cgo/gcc_riscv64.S
* Called from standard RISCV ELF psABI, where x8-x9, x18-x27, f8-f9 and * f18-f27 are callee-save, so they must be saved explicitly, along with * x1 (LR). */ .globl crosscall1 crosscall1: sd x1, -200(sp) addi sp, sp, -200 sd x8, 8(sp) sd x9, 16(sp) sd x18, 24(sp) sd x19, 32(sp) sd x20, 40(sp) sd x21, 48(sp) sd x22, 56(sp) sd x23, 64(sp) sd x24, 72(sp) sd x25, 80(sp) sd x26, 88(sp)
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon Dec 05 16:41:48 UTC 2022 - 1.6K bytes - Viewed (0) -
src/cmd/cgo/internal/test/stubtest_linux_ppc64le.S
.type toc_func, @function toc_func: addis 2,12,.TOC.-toc_func@ha addi 2,2,.TOC.-toc_func@l .localentry toc_func, .-toc_func mflr 0 std 0,16(1) stdu 1,-32(1) // Call a NOTOC function which clobbers R2. bl notoc_nor2_func nop // Call libc random. This should generate a TOC relative plt stub. bl random nop addi 1,1,32 ld 0,16(1) mtlr 0 blr
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Sep 22 15:06:17 UTC 2023 - 3.7K bytes - Viewed (0) -
src/runtime/cgo/gcc_loong64.S
* Called from standard lp64d ABI, where $r1, $r3, $r23-$r30, and $f24-$f31 * are callee-save, so they must be saved explicitly, along with $r1 (LR). */ .globl crosscall1 crosscall1: addi.d $r3, $r3, -160 st.d $r1, $r3, 0 st.d $r23, $r3, 8 st.d $r24, $r3, 16 st.d $r25, $r3, 24 st.d $r26, $r3, 32 st.d $r27, $r3, 40 st.d $r28, $r3, 48 st.d $r29, $r3, 56 st.d $r30, $r3, 64
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon Dec 05 18:57:04 UTC 2022 - 1.5K bytes - Viewed (0) -
src/cmd/link/internal/loong64/asm.go
// 0: R_LARCH_PCALA_HI20 local.moduledata o(0x1a000004) rel, _ := initfunc.AddRel(objabi.R_LOONG64_ADDR_HI) rel.SetOff(0) rel.SetSiz(4) rel.SetSym(ctxt.Moduledata) // 4: 02c00084 addi.d $a0, $a0, 0 // 4: R_LARCH_PCALA_LO12 local.moduledata o(0x02c00084) rel2, _ := initfunc.AddRel(objabi.R_LOONG64_ADDR_LO) rel2.SetOff(4) rel2.SetSiz(4) rel2.SetSym(ctxt.Moduledata) // 8: 50000000 b 0
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Feb 27 17:26:07 UTC 2024 - 7.5K bytes - Viewed (0) -
src/cmd/internal/obj/riscv/anames.go
// Code generated by stringer -i cpu.go -o anames.go -p riscv; DO NOT EDIT. package riscv import "cmd/internal/obj" var Anames = []string{ obj.A_ARCHSPECIFIC: "ADDI", "SLTI", "SLTIU", "ANDI", "ORI", "XORI", "SLLI", "SRLI", "SRAI", "LUI", "AUIPC", "ADD", "SLT", "SLTU", "AND", "OR", "XOR", "SLL", "SRL", "SUB", "SRA", "JAL", "JALR", "BEQ", "BNE",
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed Mar 20 14:19:33 UTC 2024 - 2.9K bytes - Viewed (0) -
src/runtime/cgo/gcc_linux_ppc64x.S
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu May 04 18:03:04 UTC 2023 - 2K bytes - Viewed (0) -
src/runtime/cgo/gcc_aix_ppc64.S
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Jan 24 22:38:02 UTC 2023 - 2.7K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/mips.s
// outcode(int($1), &$2, int($4), &$6); // } SLL $4, R1, R2 // LSHW imm ',' rreg // { // outcode(int($1), &$2, 0, &$4); // } SLL $4, R1 // // move immediate: macro for lui+or, addi, addis, and other combinations // // LMOVW imm ',' rreg // { // outcode(int($1), &$2, 0, &$4); // } MOVW $1, R1 MOVW $1, R1 // LMOVW ximm ',' rreg // {
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Aug 08 12:17:12 UTC 2023 - 6.7K bytes - Viewed (0)