AMOSWAPW	X5, (X6), X7			// af23530e
	AMOSWAPD	X5, (X6), X7			// af33530e
	AMOADDW		X5, (X6), X7			// af235306
	AMOADDD		X5, (X6), X7			// af335306
	AMOANDW		X5, (X6), X7			// af235366
	AMOANDD		X5, (X6), X7			// af335366
	AMOORW		X5, (X6), X7			// af235346
	AMOORD		X5, (X6), X7			// af335346
	AMOXORW		X5, (X6), X7			// af235326
	AMOXORD		X5, (X6), X7			// af335326
	AMOMAXW		X5, (X6), X7			// af2353a6

	VPBROADCASTW R14, K6, Z11                          // 62527d4e7bde
	VPBROADCASTW X9, K3, X7                            // 62d27d0b79f9
	VPBROADCASTW 99(R15)(R15*1), K3, X7                // 62927d0b79bc3f63000000
	VPBROADCASTW (DX), K3, X7                          // 62f27d0b793a
	VPBROADCASTW X7, K7, Y13                           // 62727d2f79ef
	VPBROADCASTW -17(BP)(SI*8), K7, Y13                // 62727d2f79acf5efffffff

	VRSQRT28SD X16, X24, K2, X31                       // 6222bd02cdf8
	VRSQRT28SD X12, X24, K2, X31                       // 6242bd02cdfc
	VRSQRT28SD X20, X7, K2, X31                        // 6222c50acdfc
	VRSQRT28SD X16, X7, K2, X31                        // 6222c50acdf8
	VRSQRT28SD X12, X7, K2, X31                        // 6242c50acdfc
	VRSQRT28SD X20, X20, K2, X3                        // 62b2dd02cddc

	VPGATHERDQ Y0, 0(X14*8), Y6             // c4a2fd9034f500000000
	VPGATHERDQ Y0, 664(X14*8), Y6           // c4a2fd9034f598020000
	VPGATHERDQ X2, (BP)(X7*2), X1           // c4e2e9904c7d00
	VPGATHERDQ Y2, (BP)(X7*2), Y1           // c4e2ed904c7d00
	VPGATHERDQ X12, (R13)(X14*2), X11       // c40299905c7500
	VPGATHERDQ Y12, (R13)(X14*2), Y11       // c4029d905c7500

	{"X10", "X10"},
	{"X11", "X11"},
	{"X12", "X12"},
	{"X13", "X13"},
	{"X14", "X14"},
	{"X15", "X15"},
	{"X2", "X2"},
	{"X3", "X3"},
	{"X4", "X4"},
	{"X5", "X5"},
	{"X6", "X6"},
	{"X7", "X7"},
	{"X8", "X8"},
	{"X9", "X9"},
	{"_expand_key_128<>(SB)", "_expand_key_128<>(SB)"},
	{"_seek<>(SB)", "_seek<>(SB)"},
	{"a2+16(FP)", "a2+16(FP)"},
	{"addr2+24(FP)", "addr2+24(FP)"},

X1 PXOR X11, X2 PXOR X12, X3 PXOR X13, X4 PXOR X14, X5 // Similarly if zero == 0 PCMPEQL X9, X9 MOVOU X7, X15 PANDN X9, X15 MOVOU 96(SP), X9 MOVOU 112(SP), X10 MOVOU 128(SP), X11 MOVOU 144(SP), X12 MOVOU p256one<>+0(SB), X13 MOVOU p256one<>+16(SB), X14 PAND X15, X0 PAND X15, X1 PAND X15, X2 PAND X15, X3 PAND X15, X4 PAND X15, X5 PAND X7, X9 PAND X7, X10 PAND X7, X11 PAND X7, X12 PAND X7, X13 PAND X7, X14 PXOR X9, X0 PXOR X10, X1 PXOR X11, X2 PXOR X12, X3 PXOR X13, X4 PXOR X14, X5 // Finally output...

X1 PXOR X11, X2 PXOR X12, X3 PXOR X13, X4 PXOR X14, X5 // Similarly if zero == 0 PCMPEQL X9, X9 MOVOU X7, X15 PANDN X9, X15 MOVOU 96(SP), X9 MOVOU 112(SP), X10 MOVOU 128(SP), X11 MOVOU 144(SP), X12 MOVOU p256one<>+0(SB), X13 MOVOU p256one<>+16(SB), X14 PAND X15, X0 PAND X15, X1 PAND X15, X2 PAND X15, X3 PAND X15, X4 PAND X15, X5 PAND X7, X9 PAND X7, X10 PAND X7, X11 PAND X7, X12 PAND X7, X13 PAND X7, X14 PXOR X9, X0 PXOR X10, X1 PXOR X11, X2 PXOR X12, X3 PXOR X13, X4 PXOR X14, X5 // Finally output...

    }
    return retVal;
  }

  private enum SmallEnum {
    X0,
    X1,
    X2
  }

  private enum MediumEnum {
    X0,
    X1,
    X2,
    X3,
    X4,
    X5,
    X6,
    X7,
    X8,
    X9,
    X10,
    X11,
    X12,
    X13,
    X14,
    X15,
    X16,
    X17,
    X18,
    X19,
    X20,
    X21,
    X22,
    X23,
    X24,

	CMV	X0, X5					// ERROR "cannot use register X0 in rs2"
	CMV	X5, X6, X7				// ERROR "expected no register in rs1"
	CMV	X5, X0					// ERROR "cannot use register X0 in rd"
	CMV	F1, X5					// ERROR "expected integer register in rs2"
	CMV	X5, F1					// ERROR "expected integer register in rd"
	CADD	X5, X6, X7				// ERROR "rd must be the same as rs1"
	CADD	X0, X8					// ERROR "cannot use register X0 in rs2"

	XVMOVQ		X5, -2040(R4)   // 8520e02c
	XVMOVQ		X6, y+16(FP)    // 0660c02c
	XVMOVQ		X7, x+2030(FP)  // 07d8df2c
	XVMOVQ		(R4), X2        // 8200802c
	XVMOVQ		3(R4), X3       // 830c802c
	XVMOVQ		2044(R4), X4    // 84f09f2c
	XVMOVQ		-2044(R4), X5   // 8510a02c
	XVMOVQ		y+16(FP), X6    // 0660802c
	XVMOVQ		x+2030(FP), X7  // 07d89f2c

	// Move vector element to general-purpose register: VMOVQ  <Vn>.<T>[index], Rd