DiskID   string   `msg:"id"`
	Volume   string   `msg:"v"`
	FilePath string   `msg:"fp"`
	FI       FileInfo `msg:"fi"`
}

// DeleteFileHandlerParams are parameters for DeleteFileHandler
type DeleteFileHandlerParams struct {
	DiskID   string        `msg:"id"`
	Volume   string        `msg:"v"`
	FilePath string        `msg:"fp"`
	Opts     DeleteOptions `msg:"do"`
}

	// Create maps for easy lookup of instruction names etc.
	for i, s := range x86.Register {
		register[s] = int16(i + x86.REG_AL)
	}
	// Pseudo-registers.
	register["SB"] = RSB
	register["FP"] = RFP
	register["PC"] = RPC
	if linkArch == &x86.Linkamd64 {
		// Alias g to R14
		register["g"] = x86.REGG
	}
	// Register prefix not used on this architecture.

	instructions := make(map[string]obj.As)

at the beginning, as in <code>first_arg+0(FP)</code> and <code>second_arg+8(FP)</code>.
(The meaning of the offset—offset from the frame pointer—distinct
from its use with <code>SB</code>, where it is an offset from the symbol.)
The assembler enforces this convention, rejecting plain <code>0(FP)</code> and <code>8(FP)</code>.
The actual name is semantically irrelevant but should be used to document

.idea/remote-targets.xml
.idea/libraries/Gradle*.xml
.idea/libraries/Maven*.xml
.idea/modules
.idea/runConfigurations/JPS_*.xml
.idea/runConfigurations/_JPS_*.xml
.idea/runConfigurations/PILL_*.xml
.idea/runConfigurations/_FP_*.xml
.idea/runConfigurations/_MT_*.xml
.idea/libraries
.idea/modules.xml
.idea/gradle.xml
.idea/compiler.xml
.idea/inspectionProfiles/profiles_settings.xml
.idea/.name
.idea/jarRepositories.xml

				err = msgp.WrapError(err, "DiskID")
				return
			}
		case "v":
			z.Volume, err = dc.ReadString()
			if err != nil {
				err = msgp.WrapError(err, "Volume")
				return
			}
		case "fp":
			z.FilePath, err = dc.ReadString()
			if err != nil {
				err = msgp.WrapError(err, "FilePath")
				return
			}
		case "fi":
			err = z.FI.DecodeMsg(dc)
			if err != nil {

	IMULL	AX
	IMULL	$4, CX
	IMULL	AX, BX

// LTYPEXC spec9	{ outcode(int($1), &$2); }
	CMPPD	X0, X1, 4
	CMPPD	foo+4(SB), X1, 4

// LTYPEX spec10	{ outcode(int($1), &$2); }
	PINSRD	$1, (AX), X0
	PINSRD	$2, foo+4(FP), X0

// Was bug: LOOP is a branch instruction.
	JCS	2(PC)
loop:
	LOOP	loop // LOOP

// Tests for TLS reference.
	MOVL    (TLS), AX
	MOVL    8(TLS), DX

// LTYPE0 nonnon	{ outcode(int($1), &$2); }

                final FileConfig fileConfig = new FileConfig();
                fileConfig.setId(id);
                if (id.endsWith("P")) {
                    fileConfig.setConfigParameter("config.pipeline=fp");
                }
                return OptionalEntity.of(fileConfig);
            }

            @Override
            public OptionalEntity<FileConfig> getFileConfigByName(String name) {

	}
	p.get(')')
	a.Type = obj.TYPE_MEM
	if r1 < 0 {
		// Pseudo-register reference.
		if r2 != 0 {
			p.errorf("cannot use pseudo-register in pair")
			return
		}
		// For SB, SP, and FP, there must be a name here. 0(FP) is not legal.
		if name != "PC" && a.Name == obj.NAME_NONE {
			p.errorf("cannot reference %s without a symbol", name)
		}
		p.setPseudoRegister(a, name, false, prefix)
		return
	}
	a.Reg = r1

	//
	// special
	//
	SYSCALL
	BREAK
	SYNC

	//
	// conditional move on zero/nonzero gp value
	//
	CMOVN	R1, R2, R3
	CMOVZ	R1, R2, R3

	//
	// conditional move on fp false/true
	//
	CMOVF	R1, R2
	CMOVT	R1, R2

	//
	// conditional traps
	//
	TEQ	$1, R1, R2
	TEQ	$1, R1


	//
	// other
	//
	CLO	R1, R2
	SQRTD	F0, F1

	// Pseudo-registers should not be used as scaled index.
	CALL (AX)(PC*1)                 // ERROR "invalid instruction"
	CALL (AX)(SB*1)                 // ERROR "invalid instruction"
	CALL (AX)(FP*1)                 // ERROR "invalid instruction"
	// Forbid memory operands for MOV CR/DR. See #24981.
	MOVQ CR0, (AX)                  // ERROR "invalid instruction"
	MOVQ CR2, (AX)                  // ERROR "invalid instruction"