{"_seek<>(SB)", "_seek<>(SB)"},
	{"a2+16(FP)", "a2+16(FP)"},
	{"addr2+24(FP)", "addr2+24(FP)"},
	{"asmcgocall<>(SB)", "asmcgocall<>(SB)"},
	{"b+24(FP)", "b+24(FP)"},
	{"b_len+32(FP)", "b_len+32(FP)"},
	{"racecall<>(SB)", "racecall<>(SB)"},
	{"rcv_name+20(FP)", "rcv_name+20(FP)"},
	{"retoffset+28(FP)", "retoffset+28(FP)"},
	{"runtime·_GetStdHandle(SB)", "runtime._GetStdHandle(SB)"},

	MOVW	y+65540(FP), R4			// 1e020014de8f1000c4338028
	MOVWU	y+65540(FP), R4			// 1e020014de8f1000c433802a
	MOVV	y+65540(FP), R4			// 1e020014de8f1000c433c028
	MOVB	y+65540(FP), R4			// 1e020014de8f1000c4330028
	MOVBU	y+65540(FP), R4			// 1e020014de8f1000c433002a
	MOVW	y+4097(FP), R4			// 3e000014de8f1000c4278028
	MOVWU	y+4097(FP), R4			// 3e000014de8f1000c427802a
	MOVV	y+4097(FP), R4			// 3e000014de8f1000c427c028

	MOVVF	F4, F5			// 85181d01
	MOVF	F4, F5			// 85941401
	MOVD	F4, F5			// 85981401
	MOVW	R4, result+16(FP)	// 64608029
	MOVWU	R4, result+16(FP)	// 64608029
	MOVV	R4, result+16(FP)	// 6460c029
	MOVB	R4, result+16(FP)	// 64600029
	MOVBU	R4, result+16(FP)	// 64600029
	MOVWL	R4, result+16(FP)	// 6460002f
	MOVVL	R4, result+16(FP)	// 6460802f
	MOVW	R4, 1(R5)		// a4048029
	MOVWU	R4, 1(R5)		// a4048029
	MOVV	R4, 1(R5)		// a404c029

	// Create maps for easy lookup of instruction names etc.
	for i, s := range x86.Register {
		register[s] = int16(i + x86.REG_AL)
	}
	// Pseudo-registers.
	register["SB"] = RSB
	register["FP"] = RFP
	register["PC"] = RPC
	if linkArch == &x86.Linkamd64 {
		// Alias g to R14
		register["g"] = x86.REGG
	}
	// Register prefix not used on this architecture.

	instructions := make(map[string]obj.As)

	IMULL	AX
	IMULL	$4, CX
	IMULL	AX, BX

// LTYPEXC spec9	{ outcode(int($1), &$2); }
	CMPPD	X0, X1, 4
	CMPPD	foo+4(SB), X1, 4

// LTYPEX spec10	{ outcode(int($1), &$2); }
	PINSRD	$1, (AX), X0
	PINSRD	$2, foo+4(FP), X0

// Was bug: LOOP is a branch instruction.
	JCS	2(PC)
loop:
	LOOP	loop // LOOP

// Tests for TLS reference.
	MOVL    (TLS), AX
	MOVL    8(TLS), DX

// LTYPE0 nonnon	{ outcode(int($1), &$2); }

at the beginning, as in <code>first_arg+0(FP)</code> and <code>second_arg+8(FP)</code>.
(The meaning of the offset—offset from the frame pointer—distinct
from its use with <code>SB</code>, where it is an offset from the symbol.)
The assembler enforces this convention, rejecting plain <code>0(FP)</code> and <code>8(FP)</code>.
The actual name is semantically irrelevant but should be used to document

	}
	p.get(')')
	a.Type = obj.TYPE_MEM
	if r1 < 0 {
		// Pseudo-register reference.
		if r2 != 0 {
			p.errorf("cannot use pseudo-register in pair")
			return
		}
		// For SB, SP, and FP, there must be a name here. 0(FP) is not legal.
		if name != "PC" && a.Name == obj.NAME_NONE {
			p.errorf("cannot reference %s without a symbol", name)
		}
		p.setPseudoRegister(a, name, false, prefix)
		return
	}
	a.Reg = r1

	// Pseudo-registers should not be used as scaled index.
	CALL (AX)(PC*1)                 // ERROR "invalid instruction"
	CALL (AX)(SB*1)                 // ERROR "invalid instruction"
	CALL (AX)(FP*1)                 // ERROR "invalid instruction"
	// Forbid memory operands for MOV CR/DR. See #24981.
	MOVQ CR0, (AX)                  // ERROR "invalid instruction"
	MOVQ CR2, (AX)                  // ERROR "invalid instruction"

pkg syscall (linux-386), const PR_FP_EXC_ASYNC ideal-int
pkg syscall (linux-386), const PR_FP_EXC_DISABLED ideal-int
pkg syscall (linux-386), const PR_FP_EXC_DIV ideal-int
pkg syscall (linux-386), const PR_FP_EXC_INV ideal-int
pkg syscall (linux-386), const PR_FP_EXC_NONRECOV ideal-int
pkg syscall (linux-386), const PR_FP_EXC_OVF ideal-int
pkg syscall (linux-386), const PR_FP_EXC_PRECISE ideal-int

pkg syscall (netbsd-arm64-cgo), const ETHERTYPE_HAYES = 33072
pkg syscall (netbsd-arm64-cgo), const ETHERTYPE_HAYES ideal-int
pkg syscall (netbsd-arm64-cgo), const ETHERTYPE_HIPPI_FP = 33152
pkg syscall (netbsd-arm64-cgo), const ETHERTYPE_HIPPI_FP ideal-int
pkg syscall (netbsd-arm64-cgo), const ETHERTYPE_HITACHI = 34848
pkg syscall (netbsd-arm64-cgo), const ETHERTYPE_HITACHI ideal-int