start3 := off2 + 1

	off4 := off3 + int(streamSize4)
	start4 := off3 + 1

	// We let the reverse bit readers read earlier bytes,
	// because the Huffman tables ignore bits that they don't need.

	rbr1, err := r.makeReverseBitReader(data, off1, start1-2)
	if err != nil {
		return nil, err
	}

	rbr2, err := r.makeReverseBitReader(data, off2, start2-2)
	if err != nil {
		return nil, err
	}

1. Most instructions use width suffixes of instruction names to indicate operand width rather than
using different register names.

Examples:

	ADC R24, R14, R12          <=>     adc x12, x14, x24
	ADDW R26->24, R21, R15     <=>     add w15, w21, w26, asr #24
	FCMPS F2, F3               <=>     fcmp s3, s2
	FCMPD F2, F3               <=>     fcmp d3, d2
	FCVTDH F2, F3              <=>     fcvt h3, d2

// -1 is in R20, and 1 is in R21. crxlt and crxeq must
// also be the same CR field.
#define _SETB(crxlt, crxeq, rout) \
	ISEL	crxeq,R0,R21,rout \
	ISEL	crxlt,R20,rout,rout

// A special case when it is know the comparison
// will always be not equal. The result must be -1 or 1.
#define SETB_CR0_NE(rout) \
	ISEL	CR0LT,R20,R21,rout

#define SETB_CR0(rout) _SETB(CR0LT, CR0EQ, rout)

	print("r16  ", hex(c.r16()), "\t")
	print("r17  ", hex(c.r17()), "\n")
	print("r18  ", hex(c.r18()), "\t")
	print("r19  ", hex(c.r19()), "\n")
	print("r20  ", hex(c.r20()), "\t")
	print("r21  ", hex(c.r21()), "\n")
	print("r22  ", hex(c.r22()), "\t")
	print("r23  ", hex(c.r23()), "\n")
	print("r24  ", hex(c.r24()), "\t")
	print("r25  ", hex(c.r25()), "\n")
	print("r26  ", hex(c.r26()), "\t")

	print("r16  ", hex(c.r16()), "\t")
	print("r17  ", hex(c.r17()), "\n")
	print("r18  ", hex(c.r18()), "\t")
	print("r19  ", hex(c.r19()), "\n")
	print("r20  ", hex(c.r20()), "\t")
	print("r21  ", hex(c.r21()), "\n")
	print("r22  ", hex(c.r22()), "\t")
	print("r23  ", hex(c.r23()), "\n")
	print("r24  ", hex(c.r24()), "\t")
	print("r25  ", hex(c.r25()), "\n")
	print("r26  ", hex(c.r26()), "\t")

	MOVV R11, 64(R3)
	MOVV R12, 72(R3)
	MOVV R13, 80(R3)
	MOVV R14, 88(R3)
	MOVV R15, 96(R3)
	MOVV R16, 104(R3)
	MOVV R17, 112(R3)
	MOVV R18, 120(R3)
	MOVV R19, 128(R3)
	MOVV R20, 136(R3)
	MOVV R21, 144(R3)
	MOVV R23, 152(R3)
	MOVV R24, 160(R3)
	MOVV R25, 168(R3)
	MOVV R26, 176(R3)
	MOVV R27, 184(R3)
	MOVV R28, 192(R3)
	MOVV R29, 200(R3)
	MOVV R31, 208(R3)
	MOVD F0, 216(R3)
	MOVD F1, 224(R3)

	{"R11", "R11"},
	{"R12", "R12"},
	{"R13", "R13"},
	{"R14", "R14"},
	{"R15", "R15"},
	{"R16", "R16"},
	{"R17", "R17"},
	{"R18", "R18"},
	{"R19", "R19"},
	{"R2", "R2"},
	{"R20", "R20"},
	{"R21", "R21"},
	{"R22", "R22"},
	{"R23", "R23"},
	{"R24", "R24"},
	{"R25", "R25"},
	{"R26", "R26"},
	{"R27", "R27"},
	{"R28", "R28"},
	{"R29", "R29"},
	{"R3", "R3"},
	{"R31", "R31"},
	{"R4", "R4"},

	MOVW R11, 44(R29)
	MOVW R12, 48(R29)
	MOVW R13, 52(R29)
	MOVW R14, 56(R29)
	MOVW R15, 60(R29)
	MOVW R16, 64(R29)
	MOVW R17, 68(R29)
	MOVW R18, 72(R29)
	MOVW R19, 76(R29)
	MOVW R20, 80(R29)
	MOVW R21, 84(R29)
	MOVW R22, 88(R29)
	MOVW R24, 92(R29)
	MOVW R25, 96(R29)
	MOVW R28, 100(R29)
	MOVW HI, R1
	MOVW R1, 104(R29)
	MOVW LO, R1
	MOVW R1, 108(R29)
	#ifndef GOMIPS_softfloat
	MOVW FCR31, R1

	c2 := shiftRightBy51(r2)
	c3 := shiftRightBy51(r3)
	c4 := shiftRightBy51(r4)

	rr0 := r0.lo&maskLow51Bits + c4*19
	rr1 := r1.lo&maskLow51Bits + c0
	rr2 := r2.lo&maskLow51Bits + c1
	rr3 := r3.lo&maskLow51Bits + c2
	rr4 := r4.lo&maskLow51Bits + c3

	*v = Element{rr0, rr1, rr2, rr3, rr4}
	v.carryPropagate()
}

// carryPropagateGeneric brings the limbs below 52 bits by applying the reduction

 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 * See the License for the specific language governing permissions and
 * limitations under the License.
 */
package org.gradle.integtests.tooling.r21;

import org.gradle.api.GradleException;
import org.gradle.tooling.BuildAction;
import org.gradle.tooling.BuildController;
import org.gradle.tooling.model.GradleProject;