EXTSHCC:        "extsh.",
	FABS:           "fabs",
	FABSCC:         "fabs.",
	FADD:           "fadd",
	FADDCC:         "fadd.",
	FCMPO:          "fcmpo",
	FCMPU:          "fcmpu",
	FDIV:           "fdiv",
	FDIVCC:         "fdiv.",
	FMADD:          "fmadd",
	FMADDCC:        "fmadd.",
	FMR:            "fmr",
	FMRCC:          "fmr.",
	FMSUB:          "fmsub",
	FMSUBCC:        "fmsub.",

	"FCVTDH",
	"FCVTDS",
	"FCVTHD",
	"FCVTHS",
	"FCVTSD",
	"FCVTSH",
	"FCVTZSD",
	"FCVTZSDW",
	"FCVTZSS",
	"FCVTZSSW",
	"FCVTZUD",
	"FCVTZUDW",
	"FCVTZUS",
	"FCVTZUSW",
	"FDIVD",
	"FDIVS",
	"FLDPD",
	"FLDPQ",
	"FLDPS",
	"FMADDD",
	"FMADDS",
	"FMAXD",
	"FMAXNMD",
	"FMAXNMS",
	"FMAXS",
	"FMIND",
	"FMINNMD",
	"FMINNMS",
	"FMINS",
	"FMOVD",
	"FMOVQ",

(Mul32 ...) => (MULW ...)
(Mul16 x y) => (MULW (SignExt16to32 x) (SignExt16to32 y))
(Mul8 x y)  => (MULW (SignExt8to32 x)  (SignExt8to32 y))
(Mul(64|32)F ...) => (FMUL(D|S) ...)

(Div(64|32)F ...) => (FDIV(D|S) ...)

(Div64 x y [false])  => (DIV x y)
(Div64u ...) => (DIVU ...)
(Div32 x y [false])  => (DIVW x y)
(Div32u ...) => (DIVUW ...)
(Div16 x y [false])  => (DIVW  (SignExt16to32 x) (SignExt16to32 y))

{"Name":"FDIV (vector)","Bits":"0|Q|1|0|1|1|1|0|0|sz|1|Rm:5|1|1|1|1|1|1|Rn:5|Rd:5","Arch":"Vector single-precision and double-precision variant","Syntax":"FDIV <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
{"Name":"FDIV (scalar)","Bits":"0|0|0|1|1|1|1|0|00:2|1|Rm:5|0|0|0|1|1|0|Rn:5|Rd:5","Arch":"Single-precision variant","Syntax":"FDIV <Sd>, <Sn>, <Sm>","Code":"","Alias":""},

	"RDINSTRET",
	"RDINSTRETH",
	"FRCSR",
	"FSCSR",
	"FRRM",
	"FSRM",
	"FRFLAGS",
	"FSFLAGS",
	"FSRMI",
	"FSFLAGSI",
	"FLW",
	"FSW",
	"FADDS",
	"FSUBS",
	"FMULS",
	"FDIVS",
	"FMINS",
	"FMAXS",
	"FSQRTS",
	"FMADDS",
	"FMSUBS",
	"FNMADDS",
	"FNMSUBS",
	"FCVTWS",
	"FCVTLS",
	"FCVTSW",
	"FCVTSL",
	"FCVTWUS",
	"FCVTLUS",
	"FCVTSWU",
	"FCVTSLU",

(Div8 x y) => (DIVW  (SignExt8to32 x) (SignExt8to32 y))
(Div8u x y) => (DIVWU (ZeroExt8to32 x) (ZeroExt8to32 y))

(Hmul(64|64u|32|32u) ...) => (MULH(D|DU|W|WU) ...)

(Mul(32|64)F ...) => ((FMULS|FMUL) ...)

(Div(32|64)F ...) => ((FDIVS|FDIV) ...)

// Lowering float <=> int
(Cvt32to(32|64)F x) => ((FCFIDS|FCFID) (MTVSRD (SignExt32to64 x)))
(Cvt64to(32|64)F x) => ((FCFIDS|FCFID) (MTVSRD x))

(Cvt32Fto(32|64) x) => (MFVSRD (FCTI(W|D)Z x))

(Sub64F x y) => (Select0 (FSUB x y))

(Mul64 ...) => (MULLD ...)
(Mul(32|16|8) ...) => (MULLW ...)
(Mul32F ...) => (FMULS ...)
(Mul64F ...) => (FMUL ...)
(Mul64uhilo ...) => (MLGR ...)

(Div32F ...) => (FDIVS ...)
(Div64F ...) => (FDIV ...)

(Div64 x y) => (DIVD x y)
(Div64u ...) => (DIVDU ...)
// DIVW/DIVWU has a 64-bit dividend and a 32-bit divisor,
// so a sign/zero extension of the dividend is required.

	"FCOMDPP",
	"FCOMF",
	"FCOMFP",
	"FCOMI",
	"FCOMIP",
	"FCOML",
	"FCOMLP",
	"FCOMW",
	"FCOMWP",
	"FCOS",
	"FDECSTP",
	"FDIVD",
	"FDIVDP",
	"FDIVF",
	"FDIVL",
	"FDIVRD",
	"FDIVRDP",
	"FDIVRF",
	"FDIVRL",
	"FDIVRW",
	"FDIVW",
	"FFREE",
	"FINCSTP",
	"FINIT",
	"FLD1",
	"FLDCW",
	"FLDENV",
	"FLDL2E",
	"FLDL2T",
	"FLDLG2",
	"FLDLN2",
	"FLDPI",

		return
	}
	q, r := udiv(x, y)
	q1 := x/y
	r1 := x%y
	if q1 != q {
		print("uint64(", x, "/", y, ") = ", q1, ", want ", q, "\n")
	}
	if r1 != r {
		print("uint64(", x, "%", y, ") = ", r1, ", want ", r, "\n")
	}
}

func checkuint32(x, y uint32) {
	if y == 0 {
		divzerouint32(x, y)
		modzerouint32(x, y)
		return
	}
	q, r := udiv(uint64(x), uint64(y))
	q1 := x/y

// Use of this source code is governed by a BSD-style
// license that can be found in the LICENSE file.

package runtime

import "unsafe"

// Called from compiler-generated code; declared for go vet.
func udiv()
func _div()
func _divu()
func _mod()
func _modu()

// Called from assembly only; declared for go vet.
func usplitR0()
func load_g()
func save_g()
func emptyfunc()
func _initcgo()
func read_tls_fallback()