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Results 11 - 20 of 42 for tst (0.02 sec)
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staging/src/k8s.io/apiextensions-apiserver/test/integration/validation_test.go
}, }, } for i := range tests { tst := tests[i] t.Run(tst.desc, func(t *testing.T) { // plug in schemas manifest := strings.NewReplacer( "GLOBAL_SCHEMA", toValidationJSON(tst.globalSchema), "V1BETA1_SCHEMA", toValidationJSON(tst.v1beta1Schema), "V1_SCHEMA", toValidationJSON(tst.v1Schema), "PRESERVE_UNKNOWN_FIELDS", tst.preserveUnknownFields, ).Replace(tmpl)
Registered: Sat Jun 15 01:39:40 UTC 2024 - Last Modified: Mon Apr 26 20:48:36 UTC 2021 - 63.6K bytes - Viewed (0) -
src/cmd/internal/obj/arm/anames.go
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed Oct 16 15:58:33 UTC 2019 - 1.4K bytes - Viewed (0) -
test/codegen/comparisons.go
// arm64:`ADD`,-`CMNW` // arm:`ADD`,-`CMN` c5 := b+d == 0 // not optimized to single TSTW/TST due to further use of a&d // arm64:`AND`,-`TSTW` // arm:`AND`,-`TST` // 386:`ANDL` c6 := a&d >= 0 // arm64:`TST\sR[0-9]+<<3,\sR[0-9]+` c7 := e&(f<<3) < 0 // arm64:`CMN\sR[0-9]+<<3,\sR[0-9]+` c8 := e+(f<<3) < 0 // arm64:`TST\sR[0-9],\sR[0-9]+` c9 := e&(-19) < 0 if c0 { return 1 } else if c1 {
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Apr 19 16:31:02 UTC 2024 - 15.2K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/ARMOps.go
{name: "CMNconst", argLength: 1, reg: gp1flags, asm: "CMN", aux: "Int32", typ: "Flags"}, // arg0 compare to -auxInt {name: "TST", argLength: 2, reg: gp2flags, asm: "TST", typ: "Flags", commutative: true}, // arg0 & arg1 compare to 0 {name: "TSTconst", argLength: 1, reg: gp1flags, asm: "TST", aux: "Int32", typ: "Flags"}, // arg0 & auxInt compare to 0
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Feb 24 00:21:13 UTC 2023 - 41K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/arm.s
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Dec 15 20:51:01 UTC 2023 - 69K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/ARM64latelower.rules
(ORconst [c] x) && !isARM64bitcon(uint64(c)) => (OR x (MOVDconst [c])) (XORconst [c] x) && !isARM64bitcon(uint64(c)) => (XOR x (MOVDconst [c])) (TSTconst [c] x) && !isARM64bitcon(uint64(c)) => (TST x (MOVDconst [c])) (TSTWconst [c] x) && !isARM64bitcon(uint64(c)|uint64(c)<<32) => (TSTW x (MOVDconst [int64(c)])) (CMPconst [c] x) && !isARM64addcon(c) => (CMP x (MOVDconst [c]))
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Mar 12 19:38:41 UTC 2024 - 4.1K bytes - Viewed (0) -
src/cmd/internal/obj/arm64/anames.go
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu May 18 01:40:37 UTC 2023 - 5.4K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/arm64.s
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Dec 08 03:28:17 UTC 2023 - 94.9K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/arm64enc.s
TLBI VAE1IS, R1 // 218308d5 TSTW $0x80000007, R9 // TSTW $2147483655, R9 // 3f0d0172 TST $0xfffffff0, LR // TST $4294967280, R30 // df6f7cf2 TSTW R10@>21, R2 // 5f54ca6a TST R17<<11, R24 // 1f2f11ea ANDSW $0x80000007, R9, ZR // ANDSW $2147483655, R9, ZR // 3f0d0172
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon Jul 24 01:11:41 UTC 2023 - 43.9K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/ARM.rules
(CMP x (SRA y z)) => (CMPshiftRAreg x y z) (CMP (SRA y z) x) => (InvertFlags (CMPshiftRAreg x y z)) (TST x (SLLconst [c] y)) => (TSTshiftLL x y [c]) (TST x (SRLconst [c] y)) => (TSTshiftRL x y [c]) (TST x (SRAconst [c] y)) => (TSTshiftRA x y [c]) (TST x (SLL y z)) => (TSTshiftLLreg x y z) (TST x (SRL y z)) => (TSTshiftRLreg x y z) (TST x (SRA y z)) => (TSTshiftRAreg x y z) (TEQ x (SLLconst [c] y)) => (TEQshiftLL x y [c])
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon Nov 20 17:19:36 UTC 2023 - 90.1K bytes - Viewed (0)