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Results 11 - 20 of 51 for divwe (0.07 sec)

  1. src/cmd/internal/obj/riscv/anames.go

    	"SLLIW",
    	"SRLIW",
    	"SRAIW",
    	"ADDW",
    	"SLLW",
    	"SRLW",
    	"SUBW",
    	"SRAW",
    	"LD",
    	"SD",
    	"MUL",
    	"MULH",
    	"MULHU",
    	"MULHSU",
    	"MULW",
    	"DIV",
    	"DIVU",
    	"REM",
    	"REMU",
    	"DIVW",
    	"DIVUW",
    	"REMW",
    	"REMUW",
    	"LRD",
    	"SCD",
    	"LRW",
    	"SCW",
    	"AMOSWAPD",
    	"AMOADDD",
    	"AMOANDD",
    	"AMOORD",
    	"AMOXORD",
    	"AMOMAXD",
    	"AMOMAXUD",
    	"AMOMIND",
    	"AMOMINUD",
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Wed Mar 20 14:19:33 UTC 2024
    - 2.9K bytes
    - Viewed (0)
  2. src/cmd/compile/internal/ssa/_gen/PPC64.rules

    (Div64 [false] x y) => (DIVD x y)
    (Div64u ...) => (DIVDU ...)
    (Div32 [false] x y) => (DIVW x y)
    (Div32u ...) => (DIVWU ...)
    (Div16 [false]  x y) => (DIVW  (SignExt16to32 x) (SignExt16to32 y))
    (Div16u x y) => (DIVWU (ZeroExt16to32 x) (ZeroExt16to32 y))
    (Div8 x y) => (DIVW  (SignExt8to32 x) (SignExt8to32 y))
    (Div8u x y) => (DIVWU (ZeroExt8to32 x) (ZeroExt8to32 y))
    
    (Hmul(64|64u|32|32u) ...) => (MULH(D|DU|W|WU) ...)
    
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Fri Jun 07 19:02:52 UTC 2024
    - 53.2K bytes
    - Viewed (0)
  3. src/cmd/compile/internal/ssa/_gen/S390X.rules

    (Div64u ...) => (DIVDU ...)
    // DIVW/DIVWU has a 64-bit dividend and a 32-bit divisor,
    // so a sign/zero extension of the dividend is required.
    (Div32  x y) => (DIVW  (MOVWreg x) y)
    (Div32u x y) => (DIVWU (MOVWZreg x) y)
    (Div16  x y) => (DIVW  (MOVHreg x) (MOVHreg y))
    (Div16u x y) => (DIVWU (MOVHZreg x) (MOVHZreg y))
    (Div8   x y) => (DIVW  (MOVBreg x) (MOVBreg y))
    (Div8u  x y) => (DIVWU (MOVBZreg x) (MOVBZreg y))
    
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Thu Oct 12 18:09:26 UTC 2023
    - 74.3K bytes
    - Viewed (0)
  4. docs/bucket/versioning/DESIGN.md

            }
          }
        }
      ]
    }
    ```
    
    ### v1.3+ versions
    
    Version 1.3 introduces changes to help with [faster metadata reads and updates](https://blog.min.io/minio-versioning-metadata-deep-dive/)
    
    | Entry           | Encoding                    | Content
    | ----------------|-----------------------------|----------------------------------------
    | xlHeaderVersion | msgp uint                   | header version identifier
    Registered: Sun Jun 16 00:44:34 UTC 2024
    - Last Modified: Sun Jul 17 15:43:14 UTC 2022
    - 5.8K bytes
    - Viewed (0)
  5. src/cmd/compile/internal/ssa/_gen/386Ops.go

    		{name: "DIVWU", argLength: 2, reg: gp11div, asm: "DIVW", clobberFlags: true},              // arg0 / arg1
    
    		{name: "MODL", argLength: 2, reg: gp11mod, asm: "IDIVL", aux: "Bool", clobberFlags: true}, // arg0 % arg1
    		{name: "MODW", argLength: 2, reg: gp11mod, asm: "IDIVW", aux: "Bool", clobberFlags: true}, // arg0 % arg1
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Tue Mar 14 08:10:32 UTC 2023
    - 45.1K bytes
    - Viewed (0)
  6. src/runtime/netpoll_kqueue.go

    			ts.tv_sec = 1e6
    		}
    		tp = &ts
    	}
    	var events [64]keventt
    retry:
    	n := kevent(kq, nil, 0, &events[0], int32(len(events)), tp)
    	if n < 0 {
    		// Ignore the ETIMEDOUT error for now, but try to dive deep and
    		// figure out what really happened with n == ETIMEOUT,
    		// see https://go.dev/issue/59679 for details.
    		if n != -_EINTR && n != -_ETIMEDOUT {
    			println("runtime: kevent on fd", kq, "failed with", -n)
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Fri Apr 12 21:17:22 UTC 2024
    - 4.6K bytes
    - Viewed (0)
  7. src/cmd/compile/internal/ssa/_gen/PPC64Ops.go

    		{name: "DIVD", argLength: 2, reg: gp21, asm: "DIVD", typ: "Int64"},   // arg0/arg1 (signed 64-bit)
    		{name: "DIVW", argLength: 2, reg: gp21, asm: "DIVW", typ: "Int32"},   // arg0/arg1 (signed 32-bit)
    		{name: "DIVDU", argLength: 2, reg: gp21, asm: "DIVDU", typ: "Int64"}, // arg0/arg1 (unsigned 64-bit)
    		{name: "DIVWU", argLength: 2, reg: gp21, asm: "DIVWU", typ: "Int32"}, // arg0/arg1 (unsigned 32-bit)
    
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Wed May 22 19:59:38 UTC 2024
    - 43.8K bytes
    - Viewed (0)
  8. platforms/documentation/docs/src/docs/userguide/reference/ci-systems/jenkins.adoc

    [[build_jenkins]]
    = Executing Gradle builds on Jenkins
    
    TIP: Top engineering teams using Jenkins have been able to reduce CI build time by up to 90% by using the Gradle Build Cache. https://gradle.org/training/#build-cache-deep-dive[Register here] for our Build Cache training session to learn how your team can achieve similar results.
    
    Building Gradle projects doesn't stop with the developer's machine.
    Registered: Wed Jun 12 18:38:38 UTC 2024
    - Last Modified: Mon Feb 05 18:33:11 UTC 2024
    - 6.2K bytes
    - Viewed (0)
  9. platforms/documentation/docs/src/docs/userguide/reference/ci-systems/travis-ci.adoc

    [[build_travis]]
    = Executing Gradle builds on Travis CI
    
    TIP: Top engineering teams using Travis CI have been able to reduce CI build time by up to 90% by using the Gradle Build Cache. https://gradle.org/training/#build-cache-deep-dive[Register here] for our Build Cache training session to learn how your team can achieve similar results.
    
    Building Gradle projects doesn't stop with the developer's machine.
    Registered: Wed Jun 12 18:38:38 UTC 2024
    - Last Modified: Mon Feb 05 18:33:11 UTC 2024
    - 5.8K bytes
    - Viewed (0)
  10. src/cmd/compile/internal/ssa/_gen/RISCV64.rules

    (Div(64|32)F ...) => (FDIV(D|S) ...)
    
    (Div64 x y [false])  => (DIV x y)
    (Div64u ...) => (DIVU ...)
    (Div32 x y [false])  => (DIVW x y)
    (Div32u ...) => (DIVUW ...)
    (Div16 x y [false])  => (DIVW  (SignExt16to32 x) (SignExt16to32 y))
    (Div16u x y) => (DIVUW (ZeroExt16to32 x) (ZeroExt16to32 y))
    (Div8 x y)   => (DIVW  (SignExt8to32 x)  (SignExt8to32 y))
    (Div8u x y)  => (DIVUW (ZeroExt8to32 x)  (ZeroExt8to32 y))
    
    (Hmul64 ...)  => (MULH  ...)
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Thu Mar 07 14:57:07 UTC 2024
    - 40.3K bytes
    - Viewed (0)
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