- Sort Score
- Num 10 results
- Language All
Results 11 - 20 of 22 for R5 (0.05 seconds)
-
src/cmd/asm/internal/asm/testdata/arm64.s
SWPLD R5, (RSP), R7 // e78365f8 SWPLW R5, (R6), R7 // c78065b8 SWPLW R5, (RSP), R7 // e78365b8 SWPLH R5, (R6), R7 // c7806578 SWPLH R5, (RSP), R7 // e7836578 SWPLB R5, (R6), R7 // c7806538 SWPLB R5, (RSP), R7 // e7836538
Created: Tue Dec 30 11:13:12 GMT 2025 - Last Modified: Mon Nov 10 17:34:13 GMT 2025 - 96.1K bytes - Click Count (0) -
src/cmd/asm/internal/asm/testdata/loong64enc1.s
SUB R4, R5 // a5101100 SUBW R4, R5 // a5101100 SUBV R4, R5 // a5901100 ADD R4, R5 // a5101000 ADDW R4, R5 // a5101000 ADDV R4, R5 // a5901000 AND R4, R5 // a5901400 NEGW R4, R5 // 05101100 NEGV R4, R5 // 05901100 SLL R4, R5 // a5101700 SLL R4, R5, R6 // a6101700 SRL R4, R5 // a5901700 SRL R4, R5, R6 // a6901700 SRA R4, R5 // a5101800 SRA R4, R5, R6 // a6101800 ROTR R4, R5 // a5101b00
Created: Tue Dec 30 11:13:12 GMT 2025 - Last Modified: Thu Nov 27 00:46:52 GMT 2025 - 44.5K bytes - Click Count (0) -
src/cmd/asm/internal/asm/testdata/mips64.s
// { // outcode(int($1), &$2, int($4), &$6); // } ADD R5, R9, R10 // 01255020 ADDU R13, R14, R19 // 01cd9821 ADDV R5, R9, R10 // 0125502c ADDVU R13, R14, R19 // 01cd982d // LADDW imm ',' sreg ',' rreg // { // outcode(int($1), &$2, int($4), &$6); // } ADD $15176, R14, R9 // 21c93b48 ADD $-9, R5, R8 // 20a8fff7 ADDU $10, R9, R9 // 2529000a ADDV $15176, R14, R9 // 61c93b48Created: Tue Dec 30 11:13:12 GMT 2025 - Last Modified: Tue Aug 08 12:17:12 GMT 2023 - 12.4K bytes - Click Count (0) -
src/cmd/asm/internal/asm/testdata/loong64error.s
ADDV16 $1, R4, R5 // ERROR "the constant must be a multiple of 65536." ADDV16 $65535, R4, R5 // ERROR "the constant must be a multiple of 65536." SC R4, 1(R5) // ERROR "offset must be a multiple of 4." SCV R4, 1(R5) // ERROR "offset must be a multiple of 4." LL 1(R5), R4 // ERROR "offset must be a multiple of 4."
Created: Tue Dec 30 11:13:12 GMT 2025 - Last Modified: Tue Oct 28 01:21:57 GMT 2025 - 689 bytes - Click Count (0) -
src/cmd/asm/internal/asm/testdata/arm64enc.s
CMNW $(2<<12), R5 // CMNW $8192, R5 // bf084031 CMN $(8<<12), R12 // CMN $32768, R12 // 9f2140b1 CMN R6->0, R3 // 7f0086ab CMN R6, R3 // 7f0006ab CMNW R30, R5 // bf001e2b CMNW $2, R5 // bf080031
Created: Tue Dec 30 11:13:12 GMT 2025 - Last Modified: Mon Jul 24 01:11:41 GMT 2023 - 43.9K bytes - Click Count (0) -
src/cmd/asm/internal/asm/testdata/armerror.s
XTABU R0->24, R2 // ERROR "illegal shift" XTAHU R0@>1, R2 // ERROR "illegal shift" XTAB R0>>8, R5, R2 // ERROR "illegal shift" XTAH R0<<16, R5, R2 // ERROR "illegal shift" XTABU R0->24, R5, R2 // ERROR "illegal shift" XTAHU R0@>1, R5, R2 // ERROR "illegal shift" AND.W R0, R1 // ERROR "invalid .W suffix" ORR.P R2, R3, R4 // ERROR "invalid .P suffix"
Created: Tue Dec 30 11:13:12 GMT 2025 - Last Modified: Wed Oct 23 15:18:14 GMT 2024 - 14.5K bytes - Click Count (0) -
src/cmd/asm/internal/asm/testdata/ppc64_p10.s
Created: Tue Dec 30 11:13:12 GMT 2025 - Last Modified: Thu Mar 23 20:52:57 GMT 2023 - 14.3K bytes - Click Count (0) -
src/cmd/asm/internal/asm/testdata/armv6.s
MOVFD F0, F1 // c01ab7ee MOVDF F4, F5 // c45bb7ee LDREX (R8), R9 // 9f9f98e1 LDREXB (R11), R12 // 9fcfdbe1 LDREXD (R11), R12 // 9fcfbbe1 STREX R3, (R4), R5 // STREX (R4), R3, R5 // 935f84e1 STREXB R8, (R9), g // STREXB (R9), R8, g // 98afc9e1 STREXD R8, (R9), g // STREXD (R9), R8, g // 98afa9e1 CMPF F8, F9 // c89ab4ee10faf1ee CMPD.CS F4, F5 // c45bb42e10faf12e
Created: Tue Dec 30 11:13:12 GMT 2025 - Last Modified: Wed Oct 23 15:18:14 GMT 2024 - 4.7K bytes - Click Count (0) -
doc/asm.html
<p> Load- and store-multiple instructions operate on a range of registers. The range of registers is specified by a start register and an end register. For example, <code>LMG</code> <code>(R9),</code> <code>R5,</code> <code>R7</code> would load <code>R5</code>, <code>R6</code> and <code>R7</code> with the 64-bit values at <code>0(R9)</code>, <code>8(R9)</code> and <code>16(R9)</code> respectively. </p> <p>
Created: Tue Dec 30 11:13:12 GMT 2025 - Last Modified: Fri Nov 14 19:09:46 GMT 2025 - 36.5K bytes - Click Count (0) -
lib/fips140/v1.1.0-rc1.zip
R6-R12. ADD $112, R5 // Load xk[28:35] and cipher LXVD2X (R0+R5), V1 LXVD2X (R6+R5), V2 VCIPHER V0, V1, V0 VCIPHER V0, V2, V0 // Load xk[36:43] and cipher LXVD2X (R7+R5), V1 LXVD2X (R8+R5), V2 BEQ CR1, Ldec_tail // Key size 10? VCIPHER V0, V1, V0 VCIPHER V0, V2, V0 // Load xk[44:51] and cipher LXVD2X (R9+R5), V1 LXVD2X (R10+R5), V2 BEQ CR2, Ldec_tail // Key size 12? VCIPHER V0, V1, V0 VCIPHER V0, V2, V0 // Load xk[52:59] and cipher LXVD2X (R11+R5), V1 LXVD2X (R12+R5), V2 BNE CR3, Linvalid_key_len // Not...
Created: Tue Dec 30 11:13:12 GMT 2025 - Last Modified: Thu Dec 11 16:27:41 GMT 2025 - 663K bytes - Click Count (0)