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Results 1 - 5 of 5 for VS1 (0.27 sec)

  1. src/cmd/asm/internal/asm/testdata/ppc64_p10.s

    	XVF64GER VS2, VS1, A1                   // ec8209d8
    	XVF64GERNN VS2, VS1, A1                 // ec820fd0
    	XVF64GERNP VS2, VS1, A1                 // ec820bd0
    	XVF64GERPN VS2, VS1, A1                 // ec820dd0
    	XVF64GERPP VS2, VS1, A1                 // ec8209d0
    	XVI16GER2 VS1, VS2, A1                  // ec811258
    	XVI16GER2PP VS1, VS2, A1                // ec811358
    Registered: Tue Sep 09 11:13:09 UTC 2025
    - Last Modified: Thu Mar 23 20:52:57 UTC 2023
    - 14.3K bytes
    - Viewed (0)
  2. src/cmd/asm/internal/asm/testdata/riscv64validation.s

    	VREDXORVS	X10, V2, V3			// ERROR "expected vector register in vs1 position"
    	VWREDSUMUVS	X10, V2, V3			// ERROR "expected vector register in vs1 position"
    	VWREDSUMVS	X10, V2, V3			// ERROR "expected vector register in vs1 position"
    	VFREDOSUMVS	X10, V2, V3			// ERROR "expected vector register in vs1 position"
    	VFREDUSUMVS	X10, V2, V3			// ERROR "expected vector register in vs1 position"
    Registered: Tue Sep 09 11:13:09 UTC 2025
    - Last Modified: Wed May 21 14:19:19 UTC 2025
    - 31.6K bytes
    - Viewed (0)
  3. src/cmd/asm/internal/asm/testdata/ppc64.s

    	STXVB16X VS1, (R4)              // 7c2027d8
    	STXVH8X VS1, (R4)(R5)           // 7c252758
    	STXVH8X VS1, (R4)(R0)           // 7c202758
    	STXVH8X VS1, (R4)               // 7c202758
    	STXSDX VS1, (R3)(R4)            // 7c241d98
    	STXSDX VS1, (R4)(R0)            // 7c202598
    	STXSDX VS1, (R4)                // 7c202598
    	LXSIWAX (R3)(R4), VS1           // 7c241898
    	LXSIWAX (R3)(R0), VS1           // 7c201898
    Registered: Tue Sep 09 11:13:09 UTC 2025
    - Last Modified: Thu Nov 21 18:27:17 UTC 2024
    - 51.7K bytes
    - Viewed (0)
  4. src/cmd/asm/internal/asm/operand_test.go

    	{"(R5)", "(R5)"},
    	{"(R5)(R6*1)", "(R5)(R6*1)"},
    	{"(R5+R6)", "(R5)(R6)"},
    	{"-1(R4)", "-1(R4)"},
    	{"-1(R5)", "-1(R5)"},
    	{"6(PC)", "6(PC)"},
    	{"CR7", "CR7"},
    	{"CTR", "CTR"},
    	{"VS0", "VS0"},
    	{"VS1", "VS1"},
    	{"VS2", "VS2"},
    	{"VS3", "VS3"},
    	{"VS4", "VS4"},
    	{"VS5", "VS5"},
    	{"VS6", "VS6"},
    	{"VS7", "VS7"},
    	{"VS8", "VS8"},
    	{"VS9", "VS9"},
    	{"VS10", "VS10"},
    	{"VS11", "VS11"},
    Registered: Tue Sep 09 11:13:09 UTC 2025
    - Last Modified: Tue Aug 29 18:31:05 UTC 2023
    - 23.9K bytes
    - Viewed (0)
  5. lib/fips140/v1.0.0.zip

    CR2, keysLoaded; \ ADD $64, R16; \ ADD $64, R17; \ LXVD2X (blk_key)(R16), VS13; \ LXVD2X (blk_key)(R17), VS14; \ CMP key_len, $14; \ BEQ keysLoaded; \ MOVD R0,0(R0); \ keysLoaded: // Encrypt 1 (vin) with first 9 // keys from VS1 - VS9. #define VCIPHER_1X9_KEYS(vin) \ XXLOR VS1, VS1, V23; \ XXLOR VS2, VS2, V24; \ XXLOR VS3, VS3, V25; \ XXLOR VS4, VS4, V26; \ XXLOR VS5, VS5, V27; \ VCIPHER vin, V23, vin; \ VCIPHER vin, V24, vin; \ VCIPHER vin, V25, vin; \ VCIPHER vin, V26, vin; \ VCIPHER vin, V27, vin;...
    Registered: Tue Sep 09 11:13:09 UTC 2025
    - Last Modified: Wed Jan 29 15:10:35 UTC 2025
    - 635K bytes
    - Viewed (0)
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