{name: "NEG", argLength: 1, reg: gp11, asm: "NEG"},                    // -arg0
		{name: "NEGW", argLength: 1, reg: gp11, asm: "NEGW"},                  // -arg0 of 32 bits, sign extended to 64 bits
		{name: "SUB", argLength: 2, reg: gp21, asm: "SUB"},                    // arg0 - arg1

	BEQ	R1, 2(PC)
	RET


// More JMP/JAL cases, and canonical names JMP, CALL.

	JAL	foo(SB) // CALL foo(SB)
	BEQ	R1, 2(PC)
	JMP	foo(SB)
	CALL	foo(SB)
	RET	foo(SB)

	// unary operation
	NEGW	R1, R2 // 00011023
	NEGV	R1, R2 // 0001102f

	WSBH	R1, R2 // 7c0110a0
	DSBH	R1, R2 // 7c0110a4
	DSHD	R1, R2 // 7c011164

	SEB	R1, R2 // 7c011420
	SEH	R1, R2 // 7c011620

	RET

	"MOVZWW",
	"MPSADBW",
	"MULB",
	"MULL",
	"MULPD",
	"MULPS",
	"MULQ",
	"MULSD",
	"MULSS",
	"MULW",
	"MULXL",
	"MULXQ",
	"MWAIT",
	"NEGB",
	"NEGL",
	"NEGQ",
	"NEGW",
	"NOPL",
	"NOPW",
	"NOTB",
	"NOTL",
	"NOTQ",
	"NOTW",
	"ORB",
	"ORL",
	"ORPD",
	"ORPS",
	"ORQ",
	"ORW",
	"OUTB",
	"OUTL",
	"OUTSB",
	"OUTSL",
	"OUTSW",

	ADD	R1, R2, R3, R4                                   // ERROR "illegal combination"
	BICW	R7@>33, R5, R16                                  // ERROR "shift amount out of range 0 to 31"
	NEGW	R7<<33, R5                                       // ERROR "shift amount out of range 0 to 31"
	NEGSW	R7<<33, R5                                       // ERROR "shift amount out of range 0 to 31"

(And(32|16|8) ...) => (ANDW ...)

(Or64 ...) => (OR ...)
(Or(32|16|8) ...) => (ORW ...)

(Xor64 ...) => (XOR ...)
(Xor(32|16|8) ...) => (XORW ...)

(Neg64 ...) => (NEG ...)
(Neg(32|16|8) ...) => (NEGW ...)
(Neg32F ...) => (FNEGS ...)
(Neg64F ...) => (FNEG ...)

(Com64 ...) => (NOT ...)
(Com(32|16|8) ...) => (NOTW ...)
(NOT x) => (XOR (MOVDconst [-1]) x)
(NOTW x) => (XORWconst [-1] x)

// Lowering boolean ops

		// unary ops
		{name: "NEG", argLength: 1, reg: gp11, asm: "NEG", clobberFlags: true},   // -arg0
		{name: "NEGW", argLength: 1, reg: gp11, asm: "NEGW", clobberFlags: true}, // -arg0

		{name: "NOT", argLength: 1, reg: gp11, resultInArg0: true, clobberFlags: true},  // ^arg0

	// result: (MOVDreg x)
	for {
		x := v_0
		if x.Op != OpRISCV64SUBW {
			break
		}
		v.reset(OpRISCV64MOVDreg)
		v.AddArg(x)
		return true
	}
	// match: (MOVWreg x:(NEGW _))
	// result: (MOVDreg x)
	for {
		x := v_0
		if x.Op != OpRISCV64NEGW {
			break
		}
		v.reset(OpRISCV64MOVDreg)
		v.AddArg(x)
		return true
	}
	// match: (MOVWreg x:(MULW _ _))

	MULXQ R11, R14, R11                     // c4428bf6db
	MWAIT                                   // 0f01c9
	NEGW (BX)                               // 66f71b
	NEGW (R11)                              // 6641f71b
	NEGW DX                                 // 66f7da
	NEGW R11                                // 6641f7db
	NEGL (BX)                               // f71b
	NEGL (R11)                              // 41f71b

				continue
			}
			c := auxIntToInt64(v_1.AuxInt)
			v.reset(OpS390XADDWconst)
			v.AuxInt = int32ToAuxInt(int32(c))
			v.AddArg(x)
			return true
		}
		break
	}
	// match: (ADDW x (NEGW y))
	// result: (SUBW x y)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			if v_1.Op != OpS390XNEGW {
				continue
			}
			y := v_1.Args[0]

			},
			outputs: []outputInfo{
				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
			},
		},
	},
	{
		name:   "NEGW",
		argLen: 1,
		asm:    riscv.ANEGW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
			},