MOVW	R3, 12(R29)
	MOVW	R4, 16(R29)
	MOVW	R5, 20(R29)
	MOVW	R6, 24(R29)
	MOVW	R7, 28(R29)
	MOVW	R8, 32(R29)
	MOVW	R9, 36(R29)
	MOVW	R10, 40(R29)
	MOVW	R11, 44(R29)
	MOVW	R12, 48(R29)
	MOVW	R13, 52(R29)
	MOVW	R14, 56(R29)
	MOVW	R15, 60(R29)
	MOVW	R16, 64(R29)
	MOVW	R17, 68(R29)
	MOVW	R18, 72(R29)
	MOVW	R19, 76(R29)
	MOVW	R20, 80(R29)
	// R21 already saved
	// R22 already saved.

// Be careful when hand coding regmasks.
var regNamesARM64 = []string{
	"R0",
	"R1",
	"R2",
	"R3",
	"R4",
	"R5",
	"R6",
	"R7",
	"R8",
	"R9",
	"R10",
	"R11",
	"R12",
	"R13",
	"R14",
	"R15",
	"R16",
	"R17",
	"R18", // platform register, not used
	"R19",
	"R20",
	"R21",
	"R22",
	"R23",
	"R24",
	"R25",
	"R26",
	// R27 = REGTMP not used in regalloc

	typ   string
	off   int
	size  int
	inner []*asmVar
}

var (
	asmArch386      = asmArch{name: "386", bigEndian: false, stack: "SP", lr: false}
	asmArchArm      = asmArch{name: "arm", bigEndian: false, stack: "R13", lr: true}
	asmArchArm64    = asmArch{name: "arm64", bigEndian: false, stack: "RSP", lr: true, retRegs: []string{"R0", "F0"}}

#include "textflag.h"

#define res_ptr DI
#define x_ptr SI
#define y_ptr CX

#define acc0 R8
#define acc1 R9
#define acc2 R10
#define acc3 R11
#define acc4 R12
#define acc5 R13
#define t0 R14
#define t1 R15

DATA p256const0<>+0x00(SB)/8, $0x00000000ffffffff
DATA p256const1<>+0x00(SB)/8, $0xffffffff00000001
DATA p256ordK0<>+0x00(SB)/8, $0xccd1c8aaee00bc4f

#define pTbl DI
#define ctx DX
#define ctrPtr CX
#define ptx SI
#define ks AX
#define tPtr R8
#define ptxLen R9
#define aluCTR R10
#define aluTMP R11
#define aluK R12
#define NR R13

#define increment(i) ADDL $1, aluCTR; MOVL aluCTR, aluTMP; XORL aluK, aluTMP; BSWAPL aluTMP; MOVL aluTMP, (3*4 + 8*16 + i*16)(SP)

#define ctrPtr R2
#define srcPtr R3
#define ks R4
#define tPtr R5
#define srcPtrLen R6
#define aluCTR R7
#define aluTMP R8
#define aluK R9
#define NR R10
#define H0 R11
#define H1 R12
#define curK R13
#define pTblSave R14

#define aesrndx8(K) \
	AESE	K.B16, B0.B16    \
	AESMC	B0.B16, B0.B16   \
	AESE	K.B16, B1.B16    \
	AESMC	B1.B16, B1.B16   \
	AESE	K.B16, B2.B16    \
	AESMC	B2.B16, B2.B16   \

#define b_ptr R2

#define acc0 R3
#define acc1 R4
#define acc2 R5
#define acc3 R6

#define acc4 R7
#define acc5 R8
#define acc6 R9
#define acc7 R10
#define t0 R11
#define t1 R12
#define t2 R13
#define t3 R14
#define const0 R15
#define const1 R16

#define hlp0 R17
#define hlp1 res_ptr

#define x0 R19
#define x1 R20
#define x2 R21
#define x3 R22
#define y0 R23
#define y1 R24

	*R12
}

type R6 R5
type R7 R5
type R8 R5

type R9 struct {
	*R13
	*R14
	*R15
	*R16
}

type R10 R9
type R11 R9
type R12 R9

type R13 struct {
	*R17
	*R18
	*R19
	*R20
}

type R14 R13
type R15 R13
type R16 R13

type R17 struct {
	*R21
	*R22
	*R23
	*R24
}

type R18 R17

		{"RegsAMD64.FS", Field, 0},
		{"RegsAMD64.GS", Field, 0},
		{"RegsAMD64.IP", Field, 0},
		{"RegsAMD64.R10", Field, 0},
		{"RegsAMD64.R11", Field, 0},
		{"RegsAMD64.R12", Field, 0},
		{"RegsAMD64.R13", Field, 0},
		{"RegsAMD64.R14", Field, 0},
		{"RegsAMD64.R15", Field, 0},
		{"RegsAMD64.R8", Field, 0},
		{"RegsAMD64.R9", Field, 0},
		{"RegsAMD64.SI", Field, 0},
		{"RegsAMD64.SP", Field, 0},