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Results 41 - 48 of 48 for r26 (0.02 sec)

  1. src/cmd/compile/internal/ssa/_gen/MIPSOps.go

    	"R6",
    	"R7",
    	"R8",
    	"R9",
    	"R10",
    	"R11",
    	"R12",
    	"R13",
    	"R14",
    	"R15",
    	"R16",
    	"R17",
    	"R18",
    	"R19",
    	"R20",
    	"R21",
    	"R22",
    	//REGTMP
    	"R24",
    	"R25",
    	// R26 reserved by kernel
    	// R27 reserved by kernel
    	"R28",
    	"SP",  // aka R29
    	"g",   // aka R30
    	"R31", // REGLINK
    
    	// odd FP registers contain high parts of 64-bit FP values
    	"F0",
    	"F2",
    	"F4",
    	"F6",
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Wed May 24 14:43:03 UTC 2023
    - 24K bytes
    - Viewed (0)
  2. src/cmd/compile/internal/ssa/_gen/PPC64Ops.go

    	"R9",
    	"R10",
    	"R11", // REGCTXT for closures
    	"R12",
    	"R13", // REGTLS
    	"R14",
    	"R15",
    	"R16",
    	"R17",
    	"R18",
    	"R19",
    	"R20",
    	"R21",
    	"R22",
    	"R23",
    	"R24",
    	"R25",
    	"R26",
    	"R27",
    	"R28",
    	"R29",
    	"g",   // REGG.  Using name "g" and setting Config.hasGReg makes it "just happen".
    	"R31", // REGTMP
    
    	"F0",
    	"F1",
    	"F2",
    	"F3",
    	"F4",
    	"F5",
    	"F6",
    	"F7",
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Wed May 22 19:59:38 UTC 2024
    - 43.8K bytes
    - Viewed (0)
  3. src/cmd/compile/internal/ssa/_gen/MIPS64Ops.go

    	"R8",
    	"R9",
    	"R10",
    	"R11",
    	"R12",
    	"R13",
    	"R14",
    	"R15",
    	"R16",
    	"R17",
    	"R18",
    	"R19",
    	"R20",
    	"R21",
    	"R22",
    	// R23 = REGTMP not used in regalloc
    	"R24",
    	"R25",
    	// R26 reserved by kernel
    	// R27 reserved by kernel
    	// R28 = REGSB not used in regalloc
    	"SP",  // aka R29
    	"g",   // aka R30
    	"R31", // aka REGLINK
    
    	"F0",
    	"F1",
    	"F2",
    	"F3",
    	"F4",
    	"F5",
    	"F6",
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Wed May 24 03:36:31 UTC 2023
    - 25.5K bytes
    - Viewed (0)
  4. src/runtime/asm_mips64x.s

    	MOVV	R17, 136(R29)
    	MOVV	R18, 144(R29)
    	MOVV	R19, 152(R29)
    	// R20 already saved
    	// R21 already saved.
    	MOVV	R22, 160(R29)
    	// R23 is tmp register.
    	MOVV	R24, 168(R29)
    	MOVV	R25, 176(R29)
    	// R26 is reserved by kernel.
    	// R27 is reserved by kernel.
    	// R28 is REGSB (not modified by Go code).
    	// R29 is SP.
    	// R30 is g.
    	// R31 is LR, which was saved by the prologue.
    
    	CALL	runtime·wbBufFlush(SB)
    
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Mon Nov 06 19:45:59 UTC 2023
    - 24.3K bytes
    - Viewed (0)
  5. src/cmd/asm/internal/asm/testdata/arm64error.s

    	STP	(R3, R4), 0x1234567(R27)                         // ERROR "REGTMP used in large offset store"
    	LDP	0x1234567(R27), (R3, R4)                         // ERROR "REGTMP used in large offset load"
    	STP	(R26, R27), 700(R2)                              // ERROR "cannot use REGTMP as source"
    	MOVK	$0, R10                                          // ERROR "zero shifts cannot be handled correctly"
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Fri Dec 08 03:28:17 UTC 2023
    - 37.8K bytes
    - Viewed (0)
  6. src/runtime/asm_mipsx.s

    	MOVW	R18, 72(R29)
    	MOVW	R19, 76(R29)
    	MOVW	R20, 80(R29)
    	// R21 already saved
    	// R22 already saved.
    	MOVW	R22, 84(R29)
    	// R23 is tmp register.
    	MOVW	R24, 88(R29)
    	MOVW	R25, 92(R29)
    	// R26 is reserved by kernel.
    	// R27 is reserved by kernel.
    	MOVW	R28, 96(R29)
    	// R29 is SP.
    	// R30 is g.
    	// R31 is LR, which was saved by the prologue.
    
    	CALL	runtime·wbBufFlush(SB)
    
    	MOVW	4(R29), R20
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Mon May 06 11:46:29 UTC 2024
    - 26.3K bytes
    - Viewed (0)
  7. src/crypto/internal/nistec/p256_asm_arm64.s

    #define const0 R15
    #define const1 R16
    
    #define hlp0 R17
    #define hlp1 res_ptr
    
    #define x0 R19
    #define x1 R20
    #define x2 R21
    #define x3 R22
    #define y0 R23
    #define y1 R24
    #define y2 R25
    #define y3 R26
    
    #define const2 t2
    #define const3 t3
    
    DATA p256const0<>+0x00(SB)/8, $0x00000000ffffffff
    DATA p256const1<>+0x00(SB)/8, $0xffffffff00000001
    DATA p256ordK0<>+0x00(SB)/8, $0xccd1c8aaee00bc4f
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Mon Mar 04 17:29:44 UTC 2024
    - 29.7K bytes
    - Viewed (0)
  8. src/cmd/compile/internal/ssa/_gen/ARM64.rules

    	&& s > 64 && s <= 16*64 && s%16 == 0
    	&& !config.noDuffDevice && logLargeCopy(v, s) =>
    	(DUFFCOPY [8 * (64 - s/16)] dst src mem)
    // 8 is the number of bytes to encode:
    //
    // LDP.P   16(R16), (R26, R27)
    // STP.P   (R26, R27), 16(R17)
    //
    // 64 is number of these blocks. See runtime/duff_arm64.s:duffcopy
    
    // large move uses a loop
    (Move [s] dst src mem)
    	&& s%16 == 0 && (s > 16*64 || config.noDuffDevice)
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Thu May 23 15:49:20 UTC 2024
    - 113.1K bytes
    - Viewed (0)
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