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Results 11 - 20 of 58 for Shift4 (0.14 sec)
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staging/src/k8s.io/api/rbac/v1/generated.pb.go
Registered: Sat Jun 15 01:39:40 UTC 2024 - Last Modified: Fri Mar 01 06:06:37 UTC 2024 - 77.5K bytes - Viewed (0) -
staging/src/k8s.io/api/authentication/v1/generated.pb.go
Registered: Sat Jun 15 01:39:40 UTC 2024 - Last Modified: Fri Mar 01 06:06:37 UTC 2024 - 72K bytes - Viewed (0) -
staging/src/k8s.io/api/discovery/v1/generated.pb.go
Registered: Sat Jun 15 01:39:40 UTC 2024 - Last Modified: Fri Mar 01 06:06:37 UTC 2024 - 55.6K bytes - Viewed (0) -
src/runtime/asm_amd64.s
DATA shifts<>+0x58(SB)/8, $0xffffffffffffffff DATA shifts<>+0x60(SB)/8, $0xffff0f0e0d0c0b0a DATA shifts<>+0x68(SB)/8, $0xffffffffffffffff DATA shifts<>+0x70(SB)/8, $0xff0f0e0d0c0b0a09 DATA shifts<>+0x78(SB)/8, $0xffffffffffffffff DATA shifts<>+0x80(SB)/8, $0x0f0e0d0c0b0a0908 DATA shifts<>+0x88(SB)/8, $0xffffffffffffffff DATA shifts<>+0x90(SB)/8, $0x0e0d0c0b0a090807 DATA shifts<>+0x98(SB)/8, $0xffffffffffffff0f
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Sat May 11 20:38:24 UTC 2024 - 60.4K bytes - Viewed (0) -
staging/src/k8s.io/api/certificates/v1beta1/generated.pb.go
Registered: Sat Jun 15 01:39:40 UTC 2024 - Last Modified: Fri Mar 01 06:06:37 UTC 2024 - 53.8K bytes - Viewed (0) -
staging/src/k8s.io/api/discovery/v1beta1/generated.pb.go
Registered: Sat Jun 15 01:39:40 UTC 2024 - Last Modified: Fri Mar 01 06:06:37 UTC 2024 - 54.2K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/ARM64Ops.go
// shifts {name: "SLL", argLength: 2, reg: gp21, asm: "LSL"}, // arg0 << arg1, shift amount is mod 64 {name: "SLLconst", argLength: 1, reg: gp11, asm: "LSL", aux: "Int64"}, // arg0 << auxInt, auxInt should be in the range 0 to 63. {name: "SRL", argLength: 2, reg: gp21, asm: "LSR"}, // arg0 >> arg1, unsigned, shift amount is mod 64
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu May 23 15:49:20 UTC 2024 - 58.8K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/S390XOps.go
{name: "SRW", argLength: 2, reg: sh21, asm: "SRW"}, // unsigned uint32(arg0) >> arg1, shift amount is mod 64 {name: "SRDconst", argLength: 1, reg: gp11, asm: "SRD", aux: "UInt8"}, // unsigned arg0 >> auxint, shift amount 0-63 {name: "SRWconst", argLength: 1, reg: gp11, asm: "SRW", aux: "UInt8"}, // unsigned uint32(arg0) >> auxint, shift amount 0-31 // Arithmetic shifts clobber flags.
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Feb 24 00:21:13 UTC 2023 - 52.5K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/PPC64.rules
(Rsh16x(64|32|16|8) x y) && shiftIsBounded(v) => (SRAD (MOVHreg x) y) (Rsh8x(64|32|16|8) x y) && shiftIsBounded(v) => (SRAD (MOVBreg x) y) // Unbounded shifts. Go shifts saturate to 0 or -1 when shifting beyond the number of // bits in a type, PPC64 shifts do not (see the ISA for details). // // Note, y is always non-negative. //
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Jun 07 19:02:52 UTC 2024 - 53.2K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/AMD64.rules
(Max(64|32)F <t> x y) => (Neg(64|32)F <t> (Min(64|32)F <t> (Neg(64|32)F <t> x) (Neg(64|32)F <t> y))) (CvtBoolToUint8 ...) => (Copy ...) // Lowering shifts // Unsigned shifts need to return 0 if shift amount is >= width of shifted value. // result = (arg << shift) & (shift >= argbits ? 0 : 0xffffffffffffffff) (Lsh64x(64|32|16|8) <t> x y) && !shiftIsBounded(v) => (ANDQ (SHLQ <t> x y) (SBBQcarrymask <t> (CMP(Q|L|W|B)const y [64])))
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Mar 12 19:38:41 UTC 2024 - 93.9K bytes - Viewed (0)