r12          uint32

	spr  uint32
	lrr  uint32
	pc   uint32
	cpsr uint32

	fpscr   uint32
	padding uint32

	floatNeon [16]neon128

	bvr      [8]uint32
	bcr      [8]uint32
	wvr      [1]uint32
	wcr      [1]uint32
	padding2 [2]uint32
}

func (c *context) ip() uintptr { return uintptr(c.pc) }
func (c *context) sp() uintptr { return uintptr(c.spr) }

		buf.WriteString(opcode[0:2])
		switch spr := inst.Args[0].(type) {
		case SpReg:
			switch spr {
			case 1:
				buf.WriteString("xer")
				startArg = 1
			case 8:
				buf.WriteString("lr")
				startArg = 1
			case 9:
				buf.WriteString("ctr")
				startArg = 1
			default:
				buf.WriteString("spr")
			}
		default:
			buf.WriteString("spr")
		}

	case "mfspr":

// This order should be strictly consistent to that in a.out.go
var cnames7 = []string{
	"", // C_NONE starts from 1
	"NONE",
	"REG",
	"ZREG",
	"RSP",
	"FREG",
	"VREG",
	"PAIR",
	"SHIFT",
	"EXTREG",
	"SPR",
	"SPOP",
	"COND",
	"ARNG",
	"ELEM",
	"LIST",
	"ZCON",
	"ABCON0",
	"ADDCON0",
	"ABCON",
	"AMCON",
	"ADDCON",
	"MBCON",
	"MOVCON",
	"BITCON",
	"ADDCON2",
	"LCON",
	"MOVCON2",

// license that can be found in the LICENSE file.

package ppc64

var cnames9 = []string{
	"NONE",
	"REGP",
	"REG",
	"FREGP",
	"FREG",
	"VREG",
	"VSREGP",
	"VSREG",
	"CREG",
	"CRBIT",
	"SPR",
	"MREG",
	"ZCON",
	"U1CON",
	"U2CON",
	"U3CON",
	"U4CON",
	"U5CON",
	"U8CON",
	"U15CON",
	"S16CON",
	"U16CON",
	"16CON",
	"U31CON",
	"S32CON",
	"U32CON",
	"32CON",
	"S34CON",

// license that can be found in the LICENSE file.

package arm

var cnames5 = []string{
	"NONE",
	"REG",
	"REGREG",
	"REGREG2",
	"REGLIST",
	"SHIFT",
	"SHIFTADDR",
	"FREG",
	"PSR",
	"FCR",
	"SPR",
	"RCON",
	"NCON",
	"RCON2A",
	"RCON2S",
	"SCON",
	"LCON",
	"LCONADDR",
	"ZFCON",
	"SFCON",
	"LFCON",
	"RACON",
	"LACON",
	"SBRA",
	"LBRA",
	"HAUTO",
	"FAUTO",
	"HFAUTO",

			return ppc64.REG_V0 + n, true
		}
	case "F":
		if 0 <= n && n <= 31 {
			return ppc64.REG_F0 + n, true
		}
	case "R":
		if 0 <= n && n <= 31 {
			return ppc64.REG_R0 + n, true
		}
	case "SPR":
		if 0 <= n && n <= 1024 {
			return ppc64.REG_SPR0 + n, true
		}
	}
	return 0, false

	}
	if REG_SPR0 <= r && r <= REG_SPR0+1023 {
		switch r {
		case REG_XER:
			return "XER"

		case REG_LR:
			return "LR"

		case REG_CTR:
			return "CTR"
		}

		return fmt.Sprintf("SPR(%d)", r-REG_SPR0)
	}

	if r == REG_FPSCR {
		return "FPSCR"
	}
	if r == REG_MSR {
		return "MSR"
	}

	return fmt.Sprintf("Rgok(%d)", r-obj.RBasePPC64)
}

func DRconv(a int) string {

	// Map of instruction names to enumeration.
	Instructions map[string]obj.As
	// Map of register names to enumeration.
	Register map[string]int16
	// Table of register prefix names. These are things like R for R(0) and SPR for SPR(268).
	RegisterPrefix map[string]bool
	// RegisterNumber converts R(10) into arm.REG_R10.
	RegisterNumber func(string, int16) (int16, bool)
	// Instruction is a jump.
	IsJump func(word string) bool
}

	{"R27", "R27"},
	{"R28", "R28"},
	{"R29", "R29"},
	{"R3", "R3"},
	{"R31", "R31"},
	{"R4", "R4"},
	{"R5", "R5"},
	{"R6", "R6"},
	{"R7", "R7"},
	{"R8", "R8"},
	{"R9", "R9"},
	{"SPR(269)", "SPR(269)"},
	{"a(FP)", "a(FP)"},
	{"g", "g"},
	{"ret+8(FP)", "ret+8(FP)"},
	{"runtime·abort(SB)", "runtime.abort(SB)"},
	{"·AddUint32(SB)", "pkg.AddUint32(SB)"},
	{"·trunc(SB)", "pkg.trunc(SB)"},

		}
	case Imm:
		return fmt.Sprintf("$%d", arg)
	case SpReg:
		switch arg {
		case 8:
			return "LR"
		case 9:
			return "CTR"
		}
		return fmt.Sprintf("SPR(%d)", int(arg))
	case PCRel:
		addr := pc + uint64(int64(arg))
		s, base := symname(addr)
		if s != "" && addr == base {
			return fmt.Sprintf("%s(SB)", s)
		}
		if inst.Op == BL && s != "" && (addr-base) == 8 {