"CREG",
	"CRBIT",
	"SPR",
	"MREG",
	"ZCON",
	"U1CON",
	"U2CON",
	"U3CON",
	"U4CON",
	"U5CON",
	"U8CON",
	"U15CON",
	"S16CON",
	"U16CON",
	"16CON",
	"U31CON",
	"S32CON",
	"U32CON",
	"32CON",
	"S34CON",
	"64CON",
	"SACON",
	"LACON",
	"DACON",
	"BRA",
	"BRAPIC",
	"ZOREG",
	"SOREG",
	"LOREG",
	"XOREG",
	"FPSCR",
	"LR",
	"CTR",
	"ANY",
	"GOK",
	"ADDR",

		v := c.regoff(&p.From)

		r := int(p.Reg)
		if r == 0 {
			r = int(p.To.Reg)
		}
		o1 = AOP_IRR(c.opirr(p.As), uint32(p.To.Reg), uint32(r), uint32(v))

	case 21: /* or $u32con,rx[,ry] => oris + ori (similar for xor) */
		var opu, opl uint32
		r := uint32(p.Reg)
		if r == 0 {
			r = uint32(p.To.Reg)
		}
		switch p.As {
		case AOR:
			opu, opl = OP_ORIS, OP_ORI