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Results 1 - 2 of 2 for SFCON (0.06 sec)
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src/cmd/internal/obj/arm/anames5.go
"REGREG", "REGREG2", "REGLIST", "SHIFT", "SHIFTADDR", "FREG", "PSR", "FCR", "SPR", "RCON", "NCON", "RCON2A", "RCON2S", "SCON", "LCON", "LCONADDR", "ZFCON", "SFCON", "LFCON", "RACON", "LACON", "SBRA", "LBRA", "HAUTO", "FAUTO", "HFAUTO", "SAUTO", "LAUTO", "HOREG", "FOREG", "HFOREG", "SOREG", "ROREG", "SROREG", "LOREG",
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Mar 27 19:54:44 UTC 2018 - 1.3K bytes - Viewed (0) -
src/cmd/internal/obj/arm/asm5.go
o1 |= (uint32(r) & 15) << 12 o1 |= (uint32(v) & 0xf) << 0 o1 |= (uint32(v) & 0xf0) << 12 // subf r,r,r o2 |= (uint32(r)&15)<<0 | (uint32(r)&15)<<16 | (uint32(r)&15)<<12 case 81: /* fmov sfcon,freg */ o1 = 0x0eb00a00 // VMOV imm 32 if p.As == AMOVD { o1 = 0xeeb00b00 // VMOV imm 64 } o1 |= ((uint32(p.Scond) & C_SCOND) ^ C_SCOND_XOR) << 28 o1 |= (uint32(p.To.Reg) & 15) << 12
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Dec 15 20:51:01 UTC 2023 - 79.4K bytes - Viewed (0)