func sbfx8(x int8) int64 {
	return int64(x >> 5) // arm64:"SBFX\t[$]5, R[0-9]+, [$]3"
}

// sbfx combinations.
// merge shifts with sbfiz into sbfx.
func sbfx9(x int32) int32 {
	return (x << 3) >> 4 // arm64:"SBFX\t[$]1, R[0-9]+, [$]28",-"LSL",-"ASR"
}

// merge sbfx and sign-extension into sbfx.
func sbfx10(x int32) int64 {
	c := x + 5
	return int64(c >> 20) // arm64"SBFX\t[$]20, R[0-9]+, [$]12",-"MOVW\tR[0-9]+, R[0-9]+"
}

	"REMW",
	"REV",
	"REV16",
	"REV16W",
	"REV32",
	"REVW",
	"ROR",
	"RORW",
	"SBC",
	"SBCS",
	"SBCSW",
	"SBCW",
	"SBFIZ",
	"SBFIZW",
	"SBFM",
	"SBFMW",
	"SBFX",
	"SBFXW",
	"SCVTFD",
	"SCVTFS",
	"SCVTFWD",
	"SCVTFWS",
	"SDIV",
	"SDIVW",
	"SEV",
	"SEVL",
	"SHA1C",
	"SHA1H",
	"SHA1M",
	"SHA1P",
	"SHA1SU0",
	"SHA1SU1",
	"SHA256H",

(MOVWreg (SBFX [bfc] x)) && bfc.getARM64BFwidth() <= 32 => (SBFX [bfc] x)
(MOVHreg (SBFX [bfc] x)) && bfc.getARM64BFwidth() <= 16 => (SBFX [bfc] x)
(MOVBreg (SBFX [bfc] x)) && bfc.getARM64BFwidth() <=  8 => (SBFX [bfc] x)

// sbfiz/sbfx combinations: merge shifts into bitfield ops
(SRAconst [sc] (SBFIZ [bfc] x)) && sc < bfc.getARM64BFlsb()
	=> (SBFIZ [armBFAuxInt(bfc.getARM64BFlsb()-sc, bfc.getARM64BFwidth())] x)

//
// - arg_immediate_bitmask_64_N_imms_immr:
//     a bitmask immediate for 64-bit variant and encoded in "N:imms:immr"
//
// - arg_immediate_SBFX_SBFM_64M_bitfield_width_64_imms:
//     an immediate for the <width> bitfield of SBFX 64-bit variant
//
// - arg_immediate_shift_32_implicit_inverse_imm16_hw:
//     a 32-bit immediate of the bitwise inverse of which can be encoded in "imm16:hw"
//
// - arg_cond_[Not]AllowALNV_[Invert|Normal]:

Examples:

	FMADDD F30, F20, F3, F29    <=>    fmadd d29, d3, d30, d20
	FNMSUBS F7, F25, F7, F22    <=>    fnmsub s22, s7, s7, s25

(4) BFI, BFXIL, SBFIZ, SBFX, UBFIZ, UBFX $<lsb>, <Rn>, $<width>, <Rd>

Examples:

	BFIW $16, R20, $6, R0      <=>    bfi w0, w20, #16, #6
	UBFIZ $34, R26, $5, R20    <=>    ubfiz x20, x26, #34, #5

	SADDL2:    "SADDL2",
	SADDLP:    "SADDLP",
	SADDLV:    "SADDLV",
	SADDW:     "SADDW",
	SADDW2:    "SADDW2",
	SBC:       "SBC",
	SBCS:      "SBCS",
	SBFIZ:     "SBFIZ",
	SBFM:      "SBFM",
	SBFX:      "SBFX",
	SCVTF:     "SCVTF",
	SDIV:      "SDIV",
	SEV:       "SEV",
	SEVL:      "SEVL",
	SHA1C:     "SHA1C",
	SHA1H:     "SHA1H",
	SHA1M:     "SHA1M",
	SHA1P:     "SHA1P",
	SHA1SU0:   "SHA1SU0",

			if rno <= uint16(WZR) {
				op += "W"
			}
		}
		args[1], args[2] = args[2], args[1]

	case STLXRB, STLXRH, STXRB, STXRH:
		args[1], args[2] = args[2], args[1]

	case BFI, BFXIL, SBFIZ, SBFX, UBFIZ, UBFX:
		if r, ok := inst.Args[0].(Reg); ok {
			rno := uint16(r)
			if rno <= uint16(WZR) {
				op += "W"
			}
		}
		args[1], args[2], args[3] = args[3], args[1], args[2]

	case LDAXP, LDXP:

	SBCS R5, R9, R5                            // 250105fa
	SBFIZW $9, R10, $18, R22                   // 56451713
	SBFIZ $6, R11, $15, R20                    // 74397a93
	SBFXW $8, R15, $10, R20                    // f4450813
	SBFX $2, R27, $54, R7                      // 67df4293
	SDIVW R22, R14, R9                         // c90dd61a
	SDIV R13, R21, R9                          // a90ecd9a

			break
		}
		v.reset(OpARM64SBFIZ)
		v.AuxInt = arm64BitFieldToAuxInt(armBFAuxInt(lc, 8-lc))
		v.AddArg(x)
		return true
	}
	// match: (MOVBreg (SBFX [bfc] x))
	// cond: bfc.getARM64BFwidth() <= 8
	// result: (SBFX [bfc] x)
	for {
		if v_0.Op != OpARM64SBFX {
			break
		}
		bfc := auxIntToArm64BitField(v_0.AuxInt)
		x := v_0.Args[0]
		if !(bfc.getARM64BFwidth() <= 8) {

			},
			outputs: []outputInfo{
				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
		},
	},
	{
		name:    "SBFX",
		auxType: auxARM64BitField,
		argLen:  1,
		asm:     arm64.ASBFX,
		reg: regInfo{
			inputs: []inputInfo{