//     an immediate for the <width> bitfield of SBFX 64-bit variant
//
// - arg_immediate_shift_32_implicit_inverse_imm16_hw:
//     a 32-bit immediate of the bitwise inverse of which can be encoded in "imm16:hw"
//
// - arg_cond_[Not]AllowALNV_[Invert|Normal]:
//     a standard condition, encoded in the "cond" field, excluding (NotAllow) AL and NV with
//     its least significant bit [Yes|No] inverted, e.g.
//       arg_cond_AllowALNV_Normal

  %tmp3 = "tfl.add"(%tmp2, %tmp1) { fused_activation_function = "NONE" } : (tensor<1xf32>, tensor<1xf32>) -> (tensor<1xf32>)
  %tmp4 = "tfl.while"(%tmp3) (
  {
    // cond
    ^bb0(%arg_cond: tensor<1xf32>):
    %result_cond = tfl.greater(%arg_cond, %const) : (tensor<1xf32>, tensor<1xf32>) -> tensor<1xi1>
    "tfl.yield"(%result_cond) : (tensor<1xi1>) -> ()
  },
  {
    //body
    ^bb0(%arg_body: tensor<1xf32>):

	arg_R_12_nzcv
	arg_R_16
	arg_R_16_WB
	arg_R_8
	arg_R_rotate
	arg_R_shift_R
	arg_R_shift_imm
	arg_SP
	arg_Sd
	arg_Sd_Dd
	arg_Dd_Sd
	arg_Sm
	arg_Sm_Dm
	arg_Sn
	arg_Sn_Dn
	arg_const
	arg_endian
	arg_fbits
	arg_fp_0
	arg_imm24
	arg_imm5
	arg_imm5_32
	arg_imm5_nz
	arg_imm_12at8_4at0
	arg_imm_4at16_12at0
	arg_imm_vfp
	arg_label24
	arg_label24H
	arg_label_m_12

	{0x0ff0f000, 0x03700000, 4, CMN_EQ, 0x1c04, instArgs{arg_R_16, arg_const}},                                    // CMN<c> <Rn>,#<const> cond:4|0|0|1|1|0|1|1|1|Rn:4|(0)|(0)|(0)|(0)|imm12:12
	{0x0ff00000, 0x03700000, 3, CMN_EQ, 0x1c04, instArgs{arg_R_16, arg_const}},                                    // CMN<c> <Rn>,#<const> cond:4|0|0|1|1|0|1|1|1|Rn:4|(0)|(0)|(0)|(0)|imm12:12