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doc/asm.html
Function is the outermost frame of the call stack. Traceback should stop at this function. </li> </ul> <h3 id="special-instructions">Special instructions</h3> <p> The <code>PCALIGN</code> pseudo-instruction is used to indicate that the next instruction should be aligned to a specified boundary by padding with no-op instructions. </p> <p> It is currently supported on arm64, amd64, ppc64, loong64 and riscv64.
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src/cmd/asm/internal/arch/arch.go
instructions["JZ"] = x86.AJEQ /* alternate */ instructions["MASKMOVDQU"] = x86.AMASKMOVOU instructions["MOVD"] = x86.AMOVQ instructions["MOVDQ2Q"] = x86.AMOVQ instructions["MOVNTDQ"] = x86.AMOVNTO instructions["MOVOA"] = x86.AMOVO instructions["PSLLDQ"] = x86.APSLLO instructions["PSRLDQ"] = x86.APSRLO instructions["PADDD"] = x86.APADDL // Spellings originally used in CL 97235.
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analysis/analysis-api-fe10/src/org/jetbrains/kotlin/analysis/api/descriptors/scopes/KtFe10ScopeResolution.kt
constructors.forEach { yield(it.toKtConstructorSymbol(analysisContext)) } } } internal open class KtFe10ScopeNonStaticMember( scope: MemberScope, constructors: Collection<ConstructorDescriptor>, analysisContext: Fe10AnalysisContext ) : KtFe10ScopeMember(scope, constructors, analysisContext) {
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src/cmd/asm/internal/asm/testdata/amd64error.s
VADDPD.BCST X3, X2, K1, X1 // ERROR "illegal broadcast without memory argument" // CLWB instructions: CLWB BX // ERROR "invalid instruction" // CLDEMOTE instructions: CLDEMOTE BX // ERROR "invalid instruction" // WAITPKG instructions: TPAUSE (BX) // ERROR "invalid instruction" UMONITOR (BX) // ERROR "invalid instruction"
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android/guava/src/com/google/common/util/concurrent/FuturesGetChecked.java
} private static <X extends Exception> List<Constructor<X>> preferringStringsThenThrowables( List<Constructor<X>> constructors) { return WITH_STRING_PARAM_THEN_WITH_THROWABLE_PARAM.sortedCopy(constructors); } // TODO: b/296487962 - Consider defining a total order over constructors. private static final Ordering<List<Class<?>>> ORDERING_BY_CONSTRUCTOR_PARAMETER_LIST = Ordering.natural()
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src/cmd/asm/internal/asm/testdata/riscv64.s
SW X5, 4(X6) // 23225300 SH X5, (X6) // 23105300 SH X5, 4(X6) // 23125300 SB X5, (X6) // 23005300 SB X5, 4(X6) // 23025300 // 2.7: Memory Ordering Instructions FENCE // 0f00f00f // 5.2: Integer Computational Instructions (RV64I) ADDIW $1, X5, X6 // 1b831200 SLLIW $1, X5, X6 // 1b931200 SRLIW $1, X5, X6 // 1bd31200 SRAIW $1, X5, X6 // 1bd31240 ADDW X5, X6, X7 // bb035300
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README.md
After downloading a binary release, visit https://go.dev/doc/install for installation instructions. #### Install From Source If a binary distribution is not available for your combination of operating system and architecture, visit https://go.dev/doc/install/source for source installation instructions. ### Contributing Go is the work of thousands of contributors. We appreciate your help!
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src/cmd/asm/internal/arch/ppc64.go
// one of the CMP instructions that require special handling. func IsPPC64CMP(op obj.As) bool { switch op { case ppc64.ACMP, ppc64.ACMPU, ppc64.ACMPW, ppc64.ACMPWU, ppc64.AFCMPU: return true } return false } // IsPPC64NEG reports whether the op (as defined by an ppc64.A* constant) is // one of the NEG-like instructions that require special handling. func IsPPC64NEG(op obj.As) bool {
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src/cmd/asm/internal/arch/arm.go
// one of the comparison instructions that require special handling. func IsARMCMP(op obj.As) bool { switch op { case arm.ACMN, arm.ACMP, arm.ATEQ, arm.ATST: return true } return false } // IsARMSTREX reports whether the op (as defined by an arm.A* constant) is // one of the STREX-like instructions that require special handling. func IsARMSTREX(op obj.As) bool { switch op {
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src/cmd/asm/internal/arch/loong64.go
// one of the CMP instructions that require special handling. func IsLoong64CMP(op obj.As) bool { switch op { case loong64.ACMPEQF, loong64.ACMPEQD, loong64.ACMPGEF, loong64.ACMPGED, loong64.ACMPGTF, loong64.ACMPGTD: return true } return false } // IsLoong64MUL reports whether the op (as defined by an loong64.A* constant) is // one of the MUL/DIV/REM instructions that require special handling.
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