Function is the outermost frame of the call stack. Traceback should stop at this function.
</li>
</ul>

<h3 id="special-instructions">Special instructions</h3>

<p>
The <code>PCALIGN</code> pseudo-instruction is used to indicate that the next instruction should be aligned
to a specified boundary by padding with no-op instructions.
</p>

<p>
It is currently supported on arm64, amd64, ppc64, loong64 and riscv64.

	instructions["JZ"] = x86.AJEQ   /* alternate */
	instructions["MASKMOVDQU"] = x86.AMASKMOVOU
	instructions["MOVD"] = x86.AMOVQ
	instructions["MOVDQ2Q"] = x86.AMOVQ
	instructions["MOVNTDQ"] = x86.AMOVNTO
	instructions["MOVOA"] = x86.AMOVO
	instructions["PSLLDQ"] = x86.APSLLO
	instructions["PSRLDQ"] = x86.APSRLO
	instructions["PADDD"] = x86.APADDL
	// Spellings originally used in CL 97235.

  }

  private static <X extends Exception> List<Constructor<X>> preferringStringsThenThrowables(
      List<Constructor<X>> constructors) {
    return WITH_STRING_PARAM_THEN_WITH_THROWABLE_PARAM.sortedCopy(constructors);
  }

  // TODO: b/296487962 - Consider defining a total order over constructors.
  private static final Ordering<List<Class<?>>> ORDERING_BY_CONSTRUCTOR_PARAMETER_LIST =
      Ordering.natural()

        constructors.forEach { yield(it.toKtConstructorSymbol(analysisContext)) }
    }
}

internal open class KtFe10ScopeNonStaticMember(
    scope: MemberScope,
    constructors: Collection<ConstructorDescriptor>,
    analysisContext: Fe10AnalysisContext
) : KtFe10ScopeMember(scope, constructors, analysisContext) {

	VADDPD.BCST X3, X2, K1, X1       // ERROR "illegal broadcast without memory argument"
	// CLWB instructions:
	CLWB BX                          // ERROR "invalid instruction"
	// CLDEMOTE instructions:
	CLDEMOTE BX                      // ERROR "invalid instruction"
	// WAITPKG instructions:
	TPAUSE (BX)                      // ERROR "invalid instruction"
	UMONITOR (BX)                    // ERROR "invalid instruction"

// one of the comparison instructions that require special handling.
func IsARMCMP(op obj.As) bool {
	switch op {
	case arm.ACMN, arm.ACMP, arm.ATEQ, arm.ATST:
		return true
	}
	return false
}

// IsARMSTREX reports whether the op (as defined by an arm.A* constant) is
// one of the STREX-like instructions that require special handling.
func IsARMSTREX(op obj.As) bool {
	switch op {

// one of the CMP instructions that require special handling.
func IsLoong64CMP(op obj.As) bool {
	switch op {
	case loong64.ACMPEQF, loong64.ACMPEQD, loong64.ACMPGEF, loong64.ACMPGED,
		loong64.ACMPGTF, loong64.ACMPGTD:
		return true
	}
	return false
}

// IsLoong64MUL reports whether the op (as defined by an loong64.A* constant) is
// one of the MUL/DIV/REM instructions that require special handling.

	SW	X5, 4(X6)				// 23225300
	SH	X5, (X6)				// 23105300
	SH	X5, 4(X6)				// 23125300
	SB	X5, (X6)				// 23005300
	SB	X5, 4(X6)				// 23025300

	// 2.7: Memory Ordering Instructions
	FENCE						// 0f00f00f

	// 5.2: Integer Computational Instructions (RV64I)
	ADDIW	$1, X5, X6				// 1b831200
	SLLIW	$1, X5, X6				// 1b931200
	SRLIW	$1, X5, X6				// 1bd31200
	SRAIW	$1, X5, X6				// 1bd31240
	ADDW	X5, X6, X7				// bb035300

// one of the CMP instructions that require special handling.
func IsPPC64CMP(op obj.As) bool {
	switch op {
	case ppc64.ACMP, ppc64.ACMPU, ppc64.ACMPW, ppc64.ACMPWU, ppc64.AFCMPU:
		return true
	}
	return false
}

// IsPPC64NEG reports whether the op (as defined by an ppc64.A* constant) is
// one of the NEG-like instructions that require special handling.
func IsPPC64NEG(op obj.As) bool {

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