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src/cmd/asm/internal/arch/ppc64.go
// one of the CMP instructions that require special handling. func IsPPC64CMP(op obj.As) bool { switch op { case ppc64.ACMP, ppc64.ACMPU, ppc64.ACMPW, ppc64.ACMPWU, ppc64.AFCMPU: return true } return false } // IsPPC64NEG reports whether the op (as defined by an ppc64.A* constant) is // one of the NEG-like instructions that require special handling. func IsPPC64NEG(op obj.As) bool {
Go - Registered: Tue Apr 30 11:13:12 GMT 2024 - Last Modified: Wed Sep 07 20:53:33 GMT 2022 - 2.2K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/mips64.s
// LMOVW mreg ',' rreg // { // outcode(int($1), &$2, 0, &$4); // } MOVW M1, R1 // 40010800 MOVV M1, R1 // 40210800 // // integer operations // logical instructions // shift instructions // unary instructions // // LADDW rreg ',' sreg ',' rreg // { // outcode(int($1), &$2, int($4), &$6); // } ADD R5, R9, R10 // 01255020 ADDU R13, R14, R19 // 01cd9821
Others - Registered: Tue Apr 30 11:13:12 GMT 2024 - Last Modified: Tue Aug 08 12:17:12 GMT 2023 - 12.4K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/s390x.s
Others - Registered: Tue Apr 30 11:13:12 GMT 2024 - Last Modified: Wed Nov 22 03:55:32 GMT 2023 - 21.6K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/amd64enc_extra.s
SHA256RNDS2 X0, (BX), X11 // 440f38cb1b SHA256RNDS2 X0, (R11), X11 // 450f38cb1b SHA256RNDS2 X0, X2, X11 // 440f38cbda SHA256RNDS2 X0, X11, X11 // 450f38cbdb // Rest SHA instructions tests. SHA1MSG1 (BX), X2 // 0f38c913 SHA1MSG1 (R11), X2 // 410f38c913 SHA1MSG1 X2, X2 // 0f38c9d2 SHA1MSG1 X11, X2 // 410f38c9d3 SHA1MSG1 (BX), X11 // 440f38c91b
Others - Registered: Tue Apr 30 11:13:12 GMT 2024 - Last Modified: Tue Apr 11 18:32:50 GMT 2023 - 57.6K bytes - Viewed (0) -
doc/go1.17_spec.html
<p> An implementation may combine multiple floating-point operations into a single fused operation, possibly across statements, and produce a result that differs from the value obtained by executing and rounding the instructions individually. An explicit floating-point type <a href="#Conversions">conversion</a> rounds to the precision of the target type, preventing fusion that would discard that rounding. </p> <p>
HTML - Registered: Tue May 07 11:14:38 GMT 2024 - Last Modified: Thu Apr 11 20:22:45 GMT 2024 - 211.6K bytes - Viewed (0) -
src/cmd/asm/internal/arch/arm.go
// one of the comparison instructions that require special handling. func IsARMCMP(op obj.As) bool { switch op { case arm.ACMN, arm.ACMP, arm.ATEQ, arm.ATST: return true } return false } // IsARMSTREX reports whether the op (as defined by an arm.A* constant) is // one of the STREX-like instructions that require special handling. func IsARMSTREX(op obj.As) bool { switch op {
Go - Registered: Tue Apr 30 11:13:12 GMT 2024 - Last Modified: Fri Nov 18 17:59:44 GMT 2022 - 6.1K bytes - Viewed (0) -
src/cmd/asm/internal/arch/loong64.go
// one of the CMP instructions that require special handling. func IsLoong64CMP(op obj.As) bool { switch op { case loong64.ACMPEQF, loong64.ACMPEQD, loong64.ACMPGEF, loong64.ACMPGED, loong64.ACMPGTF, loong64.ACMPGTD: return true } return false } // IsLoong64MUL reports whether the op (as defined by an loong64.A* constant) is // one of the MUL/DIV/REM instructions that require special handling.
Go - Registered: Tue Apr 30 11:13:12 GMT 2024 - Last Modified: Mon Feb 06 13:49:53 GMT 2023 - 2.1K bytes - Viewed (0) -
doc/asm.html
Function is the outermost frame of the call stack. Traceback should stop at this function. </li> </ul> <h3 id="special-instructions">Special instructions</h3> <p> The <code>PCALIGN</code> pseudo-instruction is used to indicate that the next instruction should be aligned to a specified boundary by padding with no-op instructions. </p> <p> It is currently supported on arm64, amd64, ppc64, loong64 and riscv64.
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src/cmd/asm/internal/arch/arch.go
instructions["JZ"] = x86.AJEQ /* alternate */ instructions["MASKMOVDQU"] = x86.AMASKMOVOU instructions["MOVD"] = x86.AMOVQ instructions["MOVDQ2Q"] = x86.AMOVQ instructions["MOVNTDQ"] = x86.AMOVNTO instructions["MOVOA"] = x86.AMOVO instructions["PSLLDQ"] = x86.APSLLO instructions["PSRLDQ"] = x86.APSRLO instructions["PADDD"] = x86.APADDL // Spellings originally used in CL 97235.
Go - Registered: Tue Apr 30 11:13:12 GMT 2024 - Last Modified: Tue Mar 21 06:51:28 GMT 2023 - 21.3K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/arm64.s
// license that can be found in the LICENSE file. // This input was created by taking the instruction productions in // the old assembler's (7a's) grammar and hand-writing complete // instructions for each rule, to guarantee we cover the same space. #include "../../../../../runtime/textflag.h" TEXT foo(SB), DUPOK|NOSPLIT, $-8 // arithmetic operations ADDW $1, R2, R3 ADDW R1, R2, R3
Others - Registered: Tue Apr 30 11:13:12 GMT 2024 - Last Modified: Fri Dec 08 03:28:17 GMT 2023 - 94.9K bytes - Viewed (0)