- Sort Score
- Result 10 results
- Languages All
Results 1 - 10 of 66 for mreg (0.65 sec)
-
src/cmd/asm/internal/asm/testdata/mips.s
// } ADD $4, R1 // LMUL rreg ',' rreg // { // outcode(int($1), &$2, 0, &$4); // } MUL R1, R2 // LSHW rreg ',' sreg ',' rreg // { // outcode(int($1), &$2, int($4), &$6); // } SLL R1, R2, R3 // LSHW rreg ',' rreg // { // outcode(int($1), &$2, 0, &$4); // } SLL R1, R2 // LSHW imm ',' sreg ',' rreg // { // outcode(int($1), &$2, int($4), &$6); // }Registered: Tue Dec 30 11:13:12 UTC 2025 - Last Modified: Tue Aug 08 12:17:12 UTC 2023 - 6.7K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/mips64.s
// LFADD freg ',' freg // { // outcode(int($1), &$2, 0, &$4); // } ADDD F1, F2 // LFADD freg ',' freg ',' freg // { // outcode(int($1), &$2, int($4.Reg), &$6); // } ADDD F1, F2, F3 // LFCMP freg ',' freg // { // outcode(int($1), &$2, 0, &$4); // } CMPEQD F1, F2 // // WORD // WORD $1 // 00000001 NOOP // 00000000 SYNC // 0000000f //Registered: Tue Dec 30 11:13:12 UTC 2025 - Last Modified: Tue Aug 08 12:17:12 UTC 2023 - 12.4K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/arm.s
// MULL r1,r2,(hi,lo) // // LTYPEM cond reg ',' reg ',' regreg // { // outcode($1, $2, &$3, int32($5.Reg), &$7); // } MULL R1, R2, (R3,R4) // // MULA r1,r2,r3,r4: (r1*r2+r3) & 0xffffffff . r4 // MULAW{T,B} r1,r2,r3,r4 // // LTYPEN cond reg ',' reg ',' reg ',' spreg // { // $7.Type = obj.TYPE_REGREG2; // $7.Offset = int64($9); // outcode($1, $2, &$3, int32($5.Reg), &$7); // } MULAWT R1, R2, R3, R4Registered: Tue Dec 30 11:13:12 UTC 2025 - Last Modified: Fri Dec 15 20:51:01 UTC 2023 - 69K bytes - Viewed (0) -
src/main/java/jcifs/smb1/util/mime.map
audio/x-mpegurl mp3 # MP3 Sound File audio/mpeg3 mp3 # MP3 Sound File audio/x-mpeg-3 mp3 # MP3 Sound File audio/mpeg mp2 mpa mpg mpga # MP2 Sound File audio/x-mpeg mp2 # MP2 Sound File chemical/x-pdb pdb # PDB Chemistry Model File
Registered: Sat Dec 20 13:44:44 UTC 2025 - Last Modified: Fri Mar 22 20:39:42 UTC 2019 - 5.9K bytes - Viewed (0) -
src/cmd/asm/internal/arch/loong64.go
} if isIndex { arng_type, ok = loong64ElemExtMap[ext] if !ok { return errors.New("Loong64 extension: invalid LSX/LASX arrangement type: " + ext) } a.Reg = loong64.REG_ELEM a.Reg += ((reg & loong64.EXT_REG_MASK) << loong64.EXT_REG_SHIFT) a.Reg += ((arng_type & loong64.EXT_TYPE_MASK) << loong64.EXT_TYPE_SHIFT)Registered: Tue Dec 30 11:13:12 UTC 2025 - Last Modified: Tue Aug 05 17:31:25 UTC 2025 - 3.8K bytes - Viewed (0) -
src/test/resources/jcifs/smb1/util/mime.map
audio/x-mpegurl mp3 # MP3 Sound File audio/mpeg3 mp3 # MP3 Sound File audio/x-mpeg-3 mp3 # MP3 Sound File audio/mpeg mp2 mpa mpg mpga # MP2 Sound File audio/x-mpeg mp2 # MP2 Sound File chemical/x-pdb pdb # PDB Chemistry Model File
Registered: Sat Dec 20 13:44:44 UTC 2025 - Last Modified: Thu Aug 14 05:31:44 UTC 2025 - 5.9K bytes - Viewed (0) -
src/archive/tar/testdata/ustar-file-reg.tar
Joe Tsai <******@****.***> 1443691829 -0700
Registered: Tue Dec 30 11:13:12 UTC 2025 - Last Modified: Fri Nov 06 04:31:26 UTC 2015 - 1.5K bytes - Viewed (0) -
src/cmd/asm/internal/asm/asm.go
// the CR bit. prog.Reg = a[1].Reg if a[1].Type != obj.TYPE_REG { // The CR bit is represented as a constant 0-31. Convert it to a Reg. c := p.getConstant(prog, op, &a[1]) reg, success := ppc64.ConstantToCRbit(c) if !success { p.errorf("invalid CR bit register number %d", c) } prog.Reg = reg } break }Registered: Tue Dec 30 11:13:12 UTC 2025 - Last Modified: Tue Oct 21 15:13:08 UTC 2025 - 26.7K bytes - Viewed (0) -
src/cmd/asm/internal/asm/parse.go
// Expect (SB), (FP), (PC), or (SP) p.get('(') reg := p.get(scanner.Ident).String() p.get(')') p.setPseudoRegister(a, reg, isStatic, prefix) } // setPseudoRegister sets the NAME field of addr for a pseudo-register reference such as (SB). func (p *Parser) setPseudoRegister(addr *obj.Addr, reg string, isStatic bool, prefix rune) { if addr.Reg != 0 { p.errorf("internal error: reg %s already set in pseudo", reg) } switch reg {
Registered: Tue Dec 30 11:13:12 UTC 2025 - Last Modified: Wed Nov 12 03:59:40 UTC 2025 - 37.3K bytes - Viewed (0) -
src/cmd/asm/internal/arch/arm64.go
} // ARM64RegisterShift constructs an ARM64 register with shift operation. func ARM64RegisterShift(reg, op, count int16) (int64, error) { // the base register of shift operations must be general register. if reg > arm64.REG_R31 || reg < arm64.REG_R0 { return 0, errors.New("invalid register for shift operation") } return int64(reg&31)<<16 | int64(op)<<22 | int64(uint16(count)), nil }
Registered: Tue Dec 30 11:13:12 UTC 2025 - Last Modified: Thu Oct 16 00:35:29 UTC 2025 - 6.3K bytes - Viewed (0)