atomic.Store(&traceback_cache, t)
}

// Poor mans 64-bit division.
// This is a very special function, do not use it if you are not sure what you are doing.
// int64 division is lowered into _divv() call on 386, which does not fit into nosplit functions.
// Handles overflow in a time-specific manner.
// This keeps us within no-split stack limits on 32-bit processors.
//
//go:nosplit

// license that can be found in the LICENSE file.

package runtime

import "unsafe"

// Called from compiler-generated code; declared for go vet.
func udiv()
func _div()
func _divu()
func _mod()
func _modu()

// Called from assembly only; declared for go vet.
func usplitR0()
func load_g()
func save_g()
func emptyfunc()
func _initcgo()
func read_tls_fallback()

DATA fast_udiv_tab<>+0x3c(SB)/4, $0x81828384
GLOBL fast_udiv_tab<>(SB), RODATA, $64

// The linker will pass numerator in R8
#define Rn R8
// The linker expects the result in RTMP
#define RTMP R11

TEXT runtime·_divu(SB), NOSPLIT, $16-0
	// It's not strictly true that there are no local pointers.
	// It could be that the saved registers Rq, Rr, Rs, and Rm
	// contain pointers. However, the only way this can matter

// one of the MUL/DIV/REM/MADD/MSUB instructions that require special handling.
func IsMIPSMUL(op obj.As) bool {
	switch op {
	case mips.AMUL, mips.AMULU, mips.AMULV, mips.AMULVU,
		mips.ADIV, mips.ADIVU, mips.ADIVV, mips.ADIVVU,
		mips.AREM, mips.AREMU, mips.AREMV, mips.AREMVU,
		mips.AMADD, mips.AMSUB:
		return true
	}
	return false
}

func mipsRegisterNumber(name string, n int16) (int16, bool) {
	switch name {

// one of the MUL/DIV/REM instructions that require special handling.
func IsLoong64MUL(op obj.As) bool {
	switch op {
	case loong64.AMUL, loong64.AMULU, loong64.AMULV, loong64.AMULVU,
		loong64.ADIV, loong64.ADIVU, loong64.ADIVV, loong64.ADIVVU,
		loong64.AREM, loong64.AREMU, loong64.AREMV, loong64.AREMVU:
		return true
	}
	return false
}

// IsLoong64RDTIME reports whether the op (as defined by an loong64.A*

	"SYNC",
	"SYSCALL",
	"TEQ",
	"TLBP",
	"TLBR",
	"TLBWI",
	"TLBWR",
	"TNE",
	"WORD",
	"WSBH",
	"XOR",
	"MOVV",
	"MOVVL",
	"MOVVR",
	"SLLV",
	"SRAV",
	"SRLV",
	"DIVV",
	"DIVVU",
	"REMV",
	"REMVU",
	"MULV",
	"MULVU",
	"ADDV",
	"ADDVU",
	"SUBV",
	"SUBVU",
	"DSBH",
	"DSHD",
	"TRUNCFV",
	"TRUNCDV",
	"TRUNCFW",
	"TRUNCDW",
	"MOVWU",

	"SUBU",
	"SUBW",
	"DBAR",
	"SYSCALL",
	"TEQ",
	"TNE",
	"WORD",
	"XOR",
	"MASKEQZ",
	"MASKNEZ",
	"MOVV",
	"MOVVL",
	"MOVVR",
	"SLLV",
	"SRAV",
	"SRLV",
	"ROTRV",
	"DIVV",
	"DIVVU",
	"REMV",
	"REMVU",
	"MULV",
	"MULVU",
	"MULHV",
	"MULHVU",
	"ADDV",
	"ADDVU",
	"SUBV",
	"SUBVU",
	"TRUNCFV",
	"TRUNCDV",
	"TRUNCFW",
	"TRUNCDW",
	"MOVWU",

	MULHVU	R4, R5			// a5901e00
	MULHVU	R4, R5, R6	 	// a6901e00
	REMV	R4, R5	   		// a5902200
	REMV	R4, R5, R6	   	// a6902200
	REMVU	R4, R5			// a5902300
	REMVU	R4, R5, R6		// a6902300
	DIVV	R4, R5			// a5102200
	DIVV	R4, R5, R6	   	// a6102200
	DIVVU	R4, R5	 		// a5102300
	DIVVU	R4, R5, R6		// a6102300

	MOVH	R4, result+16(FP)	// 64604029
	MOVH	R4, 1(R5)		// a4044029
	MOVH	y+8(FP), R4		// 64404028

(Div64 x y) => (Select1 (DIVV x y))
(Div64u x y) => (Select1 (DIVVU x y))
(Div32 x y) => (Select1 (DIVV (SignExt32to64 x) (SignExt32to64 y)))
(Div32u x y) => (Select1 (DIVVU (ZeroExt32to64 x) (ZeroExt32to64 y)))
(Div16 x y) => (Select1 (DIVV (SignExt16to64 x) (SignExt16to64 y)))
(Div16u x y) => (Select1 (DIVVU (ZeroExt16to64 x) (ZeroExt16to64 y)))
(Div8 x y) => (Select1 (DIVV (SignExt8to64 x) (SignExt8to64 y)))

	ADBAR
	ASYSCALL

	ATEQ
	ATNE

	AWORD

	AXOR

	AMASKEQZ
	AMASKNEZ

	// 64-bit
	AMOVV
	AMOVVL
	AMOVVR

	ASLLV
	ASRAV
	ASRLV
	AROTRV
	ADIVV
	ADIVVU

	AREMV
	AREMVU

	AMULV
	AMULVU
	AMULHV
	AMULHVU
	AADDV
	AADDVU
	ASUBV
	ASUBVU

	// 64-bit FP
	ATRUNCFV
	ATRUNCDV
	ATRUNCFW
	ATRUNCDW