RISBLGZ	$9, $24, $11, R11, R0 // ec0b09980b51

	LAA	R1, R2, 524287(R3)    // eb213fff7ff8
	LAAG	R4, R5, -524288(R6)   // eb54600080e8
	LAAL	R7, R8, 8192(R9)      // eb87900002fa
	LAALG	R10, R11, -8192(R12)  // ebbac000feea
	LAN	R1, R2, (R3)          // eb21300000f4
	LANG	R4, R5, (R6)          // eb54600000e4
	LAX	R7, R8, (R9)          // eb87900000f7
	LAXG	R10, R11, (R12)       // ebbac00000e7

//		outcode(int($1), &$2, int($4), &$6);
//	}
	ADD	R5, R9, R10	// 01255020
	ADDU	R13, R14, R19	// 01cd9821
	ADDV	R5, R9, R10	// 0125502c
	ADDVU	R13, R14, R19	// 01cd982d

//	LADDW imm ',' sreg ',' rreg
//	{
//		outcode(int($1), &$2, int($4), &$6);
//	}
	ADD	$15176, R14, R9	// 21c93b48
	ADD	$-9, R5, R8	// 20a8fff7
	ADDU	$10, R9, R9	// 2529000a
	ADDV	$15176, R14, R9	// 61c93b48
	ADDV	$-9, R5, R8	// 60a8fff7

	MOVHU.P	-0x24(R9), R8        // MOVHU.P -36(R9), R8       // b48259e0
	MOVH	-0x24(R9), R8        // MOVH -36(R9), R8          // f48259e1
	MOVH.W	-0x24(R9), R8        // MOVH.W -36(R9), R8        // f48279e1
	MOVH.P	-0x24(R9), R8        // MOVH.P -36(R9), R8        // f48259e0
	MOVHS	-0x24(R9), R8        // MOVHS -36(R9), R8         // f48259e1

	SUBSW R2.SXTH<<3, R13, R6                  // a6ad226b
	SUBS R21.UXTX<<2, R27, R4                  // 646b35eb
	SUBSW $(44<<12), R6, R9                    // SUBSW $180224, R6, R9         // c9b04071
	SUBS $(1804<<12), R13, R9                  // SUBS $7389184, R13, R9        // a9315cf1
	SUBSW R22->28, R6, R7                      // c770966b
	SUBSW R22>>28, R6, R7                      // c770566b

	{"(BP)(CX*4)", "(BP)(CX*4)"},
	{"(BP)(DX*4)", "(BP)(DX*4)"},
	{"(BP)(R8*4)", "(BP)(R8*4)"},
	{"(BX)", "(BX)"},
	{"(DI)", "(DI)"},
	{"(DI)(BX*1)", "(DI)(BX*1)"},
	{"(DX)", "(DX)"},
	{"(R9)", "(R9)"},
	{"(R9)(BX*8)", "(R9)(BX*8)"},
	{"(SI)", "(SI)"},
	{"(SI)(BX*1)", "(SI)(BX*1)"},
	{"(SI)(DX*1)", "(SI)(DX*1)"},
	{"(SP)", "(SP)"},
	{"(SP)(AX*4)", "(SP)(AX*4)"},
	{"32(SP)(BX*2)", "32(SP)(BX*2)"},

	VLD1.P	(R8)(R9.SXTX<<2), [V2.B16]                       // ERROR "invalid extended register"
	VLD1.P	(R8)(R9<<2), [V2.B16]                            // ERROR "invalid extended register"
	VST1.P	[V1.B16], (R8)(R9.UXTW)                          // ERROR "invalid extended register"
	VST1.P	[V1.B16], (R8)(R9<<1)                            // ERROR "invalid extended register"

	CASALW	R5, (RSP), R7                        // e7ffe588
	CASALH	ZR, (R5), R8                         // a8fcff48
	CASALB	R8, (R9), ZR                         // 3ffde808
	CASPD	(R30, ZR), (RSP), (R8, R9)           // e87f3e48
	CASPW	(R6, R7), (R8), (R4, R5)             // 047d2608
	CASPD	(R2, R3), (R2), (R8, R9)             // 487c2248

// RET
	RET
	RET	foo(SB)

// B/BL/B.cond cases, and canonical names JMP, CALL.

The range of registers is specified by a start register and an end register.
For example, <code>LMG</code> <code>(R9),</code> <code>R5,</code> <code>R7</code> would load
<code>R5</code>, <code>R6</code> and <code>R7</code> with the 64-bit values at
<code>0(R9)</code>, <code>8(R9)</code> and <code>16(R9)</code> respectively.
</p>

<p>
Storage-and-storage instructions such as <code>MVC</code> and <code>XC</code> are written

func (p *Parser) branch(addr *obj.Addr, target *obj.Prog) {
	*addr = obj.Addr{
		Type:  obj.TYPE_BRANCH,
		Index: 0,
	}
	addr.Val = target
}

// asmInstruction assembles an instruction.
// MOVW R9, (R10)
func (p *Parser) asmInstruction(op obj.As, cond string, a []obj.Addr) {
	// fmt.Printf("%s %+v\n", op, a)
	prog := &obj.Prog{
		Ctxt: p.ctxt,
		Pos:  p.pos(),
		As:   op,
	}
	switch len(a) {