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Results 1 - 6 of 6 for DIVUW (0.12 sec)
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src/cmd/internal/obj/riscv/anames.go
"SRLIW", "SRAIW", "ADDW", "SLLW", "SRLW", "SUBW", "SRAW", "LD", "SD", "MUL", "MULH", "MULHU", "MULHSU", "MULW", "DIV", "DIVU", "REM", "REMU", "DIVW", "DIVUW", "REMW", "REMUW", "LRD", "SCD", "LRW", "SCW", "AMOSWAPD", "AMOADDD", "AMOANDD", "AMOORD", "AMOXORD", "AMOMAXD", "AMOMAXUD", "AMOMIND", "AMOMINUD", "AMOSWAPW",
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed Mar 20 14:19:33 UTC 2024 - 2.9K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/RISCV64.rules
(Div64 x y [false]) => (DIV x y) (Div64u ...) => (DIVU ...) (Div32 x y [false]) => (DIVW x y) (Div32u ...) => (DIVUW ...) (Div16 x y [false]) => (DIVW (SignExt16to32 x) (SignExt16to32 y)) (Div16u x y) => (DIVUW (ZeroExt16to32 x) (ZeroExt16to32 y)) (Div8 x y) => (DIVW (SignExt8to32 x) (SignExt8to32 y)) (Div8u x y) => (DIVUW (ZeroExt8to32 x) (ZeroExt8to32 y)) (Hmul64 ...) => (MULH ...) (Hmul64u ...) => (MULHU ...)
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu Mar 07 14:57:07 UTC 2024 - 40.3K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/RISCV64Ops.go
{name: "DIVU", argLength: 2, reg: gp21, asm: "DIVU", typ: "UInt64"}, {name: "DIVW", argLength: 2, reg: gp21, asm: "DIVW", typ: "Int32"}, {name: "DIVUW", argLength: 2, reg: gp21, asm: "DIVUW", typ: "UInt32"}, {name: "REM", argLength: 2, reg: gp21, asm: "REM", typ: "Int64"}, // arg0 % arg1 {name: "REMU", argLength: 2, reg: gp21, asm: "REMU", typ: "UInt64"},
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu Mar 07 14:57:07 UTC 2024 - 30.7K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/riscv64.s
MULW X5, X6, X7 // bb035302 DIV X5, X6, X7 // b3435302 DIVU X5, X6, X7 // b3535302 REM X5, X6, X7 // b3635302 REMU X5, X6, X7 // b3735302 DIVW X5, X6, X7 // bb435302 DIVUW X5, X6, X7 // bb535302 REMW X5, X6, X7 // bb635302 REMUW X5, X6, X7 // bb735302 // 8.2: Load-Reserved/Store-Conditional LRW (X5), X6 // 2fa30214 LRD (X5), X6 // 2fb30214
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Mar 22 04:42:21 UTC 2024 - 16.7K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/rewriteRISCV64.go
} return false } func rewriteValueRISCV64_OpDiv16u(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Div16u x y) // result: (DIVUW (ZeroExt16to32 x) (ZeroExt16to32 y)) for { x := v_0 y := v_1 v.reset(OpRISCV64DIVUW) v0 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32) v0.AddArg(x)
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu Mar 07 14:57:07 UTC 2024 - 205.1K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/opGen.go
}, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "DIVUW", argLen: 2, asm: riscv.ADIVUW, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu May 23 15:49:20 UTC 2024 - 1M bytes - Viewed (0)