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src/cmd/asm/internal/asm/testdata/mips64.s
// { // outcode(int($1), &$2, 0, &$4); // } SUB R14, R13 // 01ae6822 SUBU R14, R13 // 01ae6823 SUBV R4, R3 // 0064182e SUBVU R4, R3 // 0064182f // LSUBW imm ',' rreg // { // outcode(int($1), &$2, 0, &$4); // } SUB $6512, R13 // 21ade690 SUB $-6512, R13 // 21ad1970 SUBU $6512, R13 // 25ade690 SUBV $9531, R16 // 6210dac5 SUBV $-9531, R13 // 61ad253b SUBVU $9531, R16 // 6610dac5
Registered: Tue Nov 05 11:13:11 UTC 2024 - Last Modified: Tue Aug 08 12:17:12 UTC 2023 - 12.4K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/loong64enc1.s
AMANDV R14, (R13), R12 // acb96238 AMORW R14, (R13), R12 // ac396338 AMORV R14, (R13), R12 // acb96338 AMXORW R14, (R13), R12 // ac396438 AMXORV R14, (R13), R12 // acb96438 AMMAXW R14, (R13), R12 // ac396538 AMMAXV R14, (R13), R12 // acb96538 AMMINW R14, (R13), R12 // ac396638 AMMINV R14, (R13), R12 // acb96638 AMMAXWU R14, (R13), R12 // ac396738 AMMAXVU R14, (R13), R12 // acb96738
Registered: Tue Nov 05 11:13:11 UTC 2024 - Last Modified: Sat Nov 02 01:36:19 UTC 2024 - 11.6K bytes - Viewed (0) -
src/cmd/asm/internal/asm/operand_test.go
{"-12(R4)", "-12(R4)"}, {"0(PC)", "0(PC)"}, {"1024", "1024"}, {"12(R(1))", "12(R1)"}, {"12(R13)", "12(R13)"}, {"R0", "R0"}, {"R0->(32-1)", "R0->31"}, {"R0<<R1", "R0<<R1"}, {"R0>>R(1)", "R0>>R1"}, {"R0@>(32-1)", "R0@>31"}, {"R1", "R1"}, {"R11", "R11"}, {"R12", "R12"}, {"R13", "R13"}, {"R14", "R14"}, {"R15", "R15"}, {"R1<<2(R3)", "R1<<2(R3)"}, {"R(1)<<2(R(3))", "R1<<2(R3)"},
Registered: Tue Nov 05 11:13:11 UTC 2024 - Last Modified: Tue Aug 29 18:31:05 UTC 2023 - 23.9K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/arm64enc.s
//TODO LDTR -0x1e(R3), R4 // 64285eb8 //TODO LDTR -0xe5(R3), R10 // 6ab851f8 //TODO LDTRB 0xf0(R13), R10 // aa094f38 //TODO LDTRH 0xe8(R13), R23 // b7894e78 //TODO LDTRSB -0x24(R20), R5 // 85cadd38 //TODO LDTRSB -0x75(R9), R13 // 2db99838 //TODO LDTRSH 0xef(R3), LR // 7ef8ce78 //TODO LDTRSH 0x96(R19), R24 // 786a8978
Registered: Tue Nov 05 11:13:11 UTC 2024 - Last Modified: Mon Jul 24 01:11:41 UTC 2023 - 43.9K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/amd64enc_extra.s
VPGATHERQQ Y2, (BP)(Y7*2), Y1 // c4e2ed914c7d00 VPGATHERQQ X12, (R13)(X14*2), X11 // c40299915c7500 VPGATHERQQ Y12, (R13)(Y14*2), Y11 // c4029d915c7500 VPGATHERQQ X2, (BP)(X7*2), X1 // c4e2e9914c7d00 VPGATHERQQ Y2, (BP)(Y7*2), Y1 // c4e2ed914c7d00 VPGATHERQQ X12, (R13)(X14*2), X11 // c40299915c7500 VPGATHERQQ Y12, (R13)(Y14*2), Y11 // c4029d915c7500
Registered: Tue Nov 05 11:13:11 UTC 2024 - Last Modified: Tue Apr 11 18:32:50 UTC 2023 - 57.6K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/arm64.s
CSINV HS, R1, R2, R3 // 232082da CSINVW MI, R2, ZR, R2 // 42409f5a CINC EQ, R4, R9 // 8914849a CINCW PL, R2, ZR // 5f44821a CINV PL, R11, R22 // 76418bda CINVW LS, R7, R13 // ed80875a CNEG LS, R13, R7 // a7858dda CNEGW EQ, R8, R13 // 0d15885a // atomic ops LDARB (R25), R2 // 22ffdf08 LDARH (R5), R7 // a7fcdf48
Registered: Tue Nov 05 11:13:11 UTC 2024 - Last Modified: Wed Jul 24 18:45:14 UTC 2024 - 95.2K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/arm64error.s
VLD1 (R8)(R13), [V2.B16] // ERROR "illegal combination" VLD1 8(R9), [V2.B16] // ERROR "illegal combination" VST1 [V1.B16], (R8)(R13) // ERROR "illegal combination" VST1 [V1.B16], 9(R2) // ERROR "illegal combination"
Registered: Tue Nov 05 11:13:11 UTC 2024 - Last Modified: Fri Dec 08 03:28:17 UTC 2023 - 37.8K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/ppc64_p10.s
PSTH R1, $1, 12345678(R2) // 061000bcb022614e PSTQ R2, $1, 12345678(R2) // 041000bcf042614e PSTW R1, $1, 12345678(R2) // 061000bc9022614e PSTW R24, $0, 45(R13) // 06000000930d002d PSTXSD V1, $1, 12345678(R2) // 041000bcb822614e PSTXSSP V1, $1, 1234567890(R0) // 04104996bc2002d2 PSTXSSP V1, $1, 1234567890(R1) // 04104996bc2102d2
Registered: Tue Nov 05 11:13:11 UTC 2024 - Last Modified: Thu Mar 23 20:52:57 UTC 2023 - 14.3K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/amd64error.s
EXTRACTPS $4, X2, (BX) // ERROR "invalid instruction" EXTRACTPS $-1, X2, (BX) // ERROR "invalid instruction" // VSIB addressing does not permit non-vector (X/Y) // scaled index register. VPGATHERDQ X12,(R13)(AX*2), X11 // ERROR "invalid instruction" VPGATHERDQ X2, 664(BX*1), X1 // ERROR "invalid instruction" VPGATHERDQ Y2, (BP)(AX*2), Y1 // ERROR "invalid instruction" VPGATHERDQ Y5, 664(DX*8), Y6 // ERROR "invalid instruction"
Registered: Tue Nov 05 11:13:11 UTC 2024 - Last Modified: Wed Jun 14 00:03:57 UTC 2023 - 8.9K bytes - Viewed (0) -
src/cmd/asm/internal/arch/arch.go
} register["LR"] = s390x.REG_LR // Pseudo-registers. register["SB"] = RSB register["FP"] = RFP register["PC"] = RPC // Avoid unintentionally clobbering g using R13. delete(register, "R13") register["g"] = s390x.REG_R13 registerPrefix := map[string]bool{ "AR": true, "F": true, "R": true, } instructions := make(map[string]obj.As) for i, s := range obj.Anames {
Registered: Tue Nov 05 11:13:11 UTC 2024 - Last Modified: Thu Oct 24 12:32:56 UTC 2024 - 21.5K bytes - Viewed (0)