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Results 1 - 8 of 8 for FCMPD (0.06 sec)
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src/cmd/internal/obj/arm64/anames.go
"DWORD", "EON", "EONW", "EOR", "EORW", "ERET", "EXTR", "EXTRW", "FABSD", "FABSS", "FADDD", "FADDS", "FCCMPD", "FCCMPED", "FCCMPES", "FCCMPS", "FCMPD", "FCMPED", "FCMPES", "FCMPS", "FCSELD", "FCSELS", "FCVTDH", "FCVTDS", "FCVTHD", "FCVTHS", "FCVTSD", "FCVTSH", "FCVTZSD", "FCVTZSDW", "FCVTZSS", "FCVTZSSW",
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu May 18 01:40:37 UTC 2023 - 5.4K bytes - Viewed (0) -
test/codegen/floats.go
// riscv64:"FMSUBD\t" return x*y - z } func FusedSub64_b(x, y, z float64) float64 { // arm64:"FMSUBD" // riscv64:"FNMSUBD\t" return z - x*y } func Cmp(f float64) bool { // arm64:"FCMPD","(BGT|BLE|BMI|BPL)",-"CSET\tGT",-"CBZ" return f > 4 || f < -4 } func CmpZero64(f float64) bool { // s390x:"LTDBR",-"FCMPU" return f <= 0 } func CmpZero32(f float32) bool {
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu Apr 04 15:24:29 UTC 2024 - 4.9K bytes - Viewed (0) -
src/cmd/internal/obj/arm64/doc.go
using different register names. Examples: ADC R24, R14, R12 <=> adc x12, x14, x24 ADDW R26->24, R21, R15 <=> add w15, w21, w26, asr #24 FCMPS F2, F3 <=> fcmp s3, s2 FCMPD F2, F3 <=> fcmp d3, d2 FCVTDH F2, F3 <=> fcvt h3, d2 2. Go uses .P and .W suffixes to indicate post-increment and pre-increment. Examples:
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon Aug 07 00:21:42 UTC 2023 - 9.6K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/arm64enc.s
//TODO VFCMLT $0, V8.S4, V7.S4 // 07e9a04e FCMPS F3, F17 // 2022231e FCMPS $(0.0), F8 // 0821201e FCMPD F11, F27 // 60236b1e FCMPD $(0.0), F25 // 2823601e FCMPES F16, F30 // d023301e FCMPES $(0.0), F29 // b823201e
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon Jul 24 01:11:41 UTC 2023 - 43.9K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/ARM64Ops.go
{name: "FCMPD", argLength: 2, reg: fp2flags, asm: "FCMPD", typ: "Flags"}, // arg0 compare to arg1, float64 {name: "FCMPS0", argLength: 1, reg: fp1flags, asm: "FCMPS", typ: "Flags"}, // arg0 compare to 0, float32 {name: "FCMPD0", argLength: 1, reg: fp1flags, asm: "FCMPD", typ: "Flags"}, // arg0 compare to 0, float64 // shifted ops
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu May 23 15:49:20 UTC 2024 - 58.8K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/ARM64.rules
// Optimize comparison between a floating-point value and 0.0 with "FCMP $(0.0), Fn" (FCMPS x (FMOVSconst [0])) => (FCMPS0 x) (FCMPS (FMOVSconst [0]) x) => (InvertFlags (FCMPS0 x)) (FCMPD x (FMOVDconst [0])) => (FCMPD0 x) (FCMPD (FMOVDconst [0]) x) => (InvertFlags (FCMPD0 x)) // CSEL needs a flag-generating argument. Synthesize a TSTW if necessary.
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu May 23 15:49:20 UTC 2024 - 113.1K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/rewriteARM64.go
v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (FCMPD x (FMOVDconst [0])) // result: (FCMPD0 x) for { x := v_0 if v_1.Op != OpARM64FMOVDconst || auxIntToFloat64(v_1.AuxInt) != 0 { break } v.reset(OpARM64FCMPD0) v.AddArg(x) return true } // match: (FCMPD (FMOVDconst [0]) x) // result: (InvertFlags (FCMPD0 x)) for {
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu May 23 15:49:20 UTC 2024 - 608.6K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/opGen.go
{1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FCMPD", argLen: 2, asm: arm64.AFCMPD, reg: regInfo{ inputs: []inputInfo{
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu May 23 15:49:20 UTC 2024 - 1M bytes - Viewed (0)