ADDU	$65536, R4, R5		// 1e02001485781000
	ADDU	$4096, R4, R5		// 3e00001485781000
	ADDU	$65536, R4		// 1e02001484781000
	ADDU	$4096, R4		// 3e00001484781000
	ADDVU	$65536, R4, R5		// 1e02001485f81000
	ADDVU	$4096, R4, R5		// 3e00001485f81000
	ADDVU	$65536, R4		// 1e02001484f81000
	ADDVU	$4096, R4		// 3e00001484f81000
	OR	$65536, R4, R5		// 1e02001485781500
	OR	$4096, R4, R5		// 3e00001485781500
	OR	$65536, R4		// 1e02001484781500

	MOVV	8(R6), R17
	ADDV	$16, R4
	ADDV	$16, R6
	SUBVU	$1, R14
	BEQ	R16, R17, chunk16_loop
	SUBV	$8, R4
	SUBV	$8, R6

byte_loop:
	BEQ	R4, R12, samebytes
	MOVBU	(R4), R8
	ADDVU	$1, R4
	MOVBU	(R6), R9
	ADDVU	$1, R6
	BEQ	R8, R9, byte_loop

byte_cmp:
	SGTU	R8, R9, R4 // R12 = 1 if (R8 > R9)
	BNE	R0, R4, ret
	MOVV	$-1, R4
	JMP	ret

samebytes:
	SGTU	R5, R7, R8
	SGTU	R7, R5, R9

	"TNE",
	"WORD",
	"WSBH",
	"XOR",
	"MOVV",
	"MOVVL",
	"MOVVR",
	"SLLV",
	"SRAV",
	"SRLV",
	"DIVV",
	"DIVVU",
	"REMV",
	"REMVU",
	"MULV",
	"MULVU",
	"ADDV",
	"ADDVU",
	"SUBV",
	"SUBVU",
	"DSBH",
	"DSHD",
	"TRUNCFV",
	"TRUNCDV",
	"TRUNCFW",
	"TRUNCDW",
	"MOVWU",
	"MOVFV",
	"MOVDV",
	"MOVVF",
	"MOVVD",
	"VMOVB",
	"VMOVH",
	"VMOVW",

	"MOVV",
	"MOVVL",
	"MOVVR",
	"SLLV",
	"SRAV",
	"SRLV",
	"ROTRV",
	"DIVV",
	"DIVVU",
	"REMV",
	"REMVU",
	"MULV",
	"MULVU",
	"MULHV",
	"MULHVU",
	"ADDV",
	"ADDVU",
	"SUBV",
	"SUBVU",
	"TRUNCFV",
	"TRUNCDV",
	"TRUNCFW",
	"TRUNCDW",
	"MOVWU",
	"MOVFV",
	"MOVDV",
	"MOVVF",
	"MOVVD",
	"AMSWAPB",
	"AMSWAPH",
	"AMSWAPW",
	"AMSWAPV",

	ADDU	R13, R14, R19	// 01cd9821
	ADDV	R5, R9, R10	// 0125502c
	ADDVU	R13, R14, R19	// 01cd982d

//	LADDW imm ',' sreg ',' rreg
//	{
//		outcode(int($1), &$2, int($4), &$6);
//	}
	ADD	$15176, R14, R9	// 21c93b48
	ADD	$-9, R5, R8	// 20a8fff7
	ADDU	$10, R9, R9	// 2529000a
	ADDV	$15176, R14, R9	// 61c93b48
	ADDV	$-9, R5, R8	// 60a8fff7
	ADDVU	$10, R9, R9	// 6529000a

//	LADDW rreg ',' rreg
//	{

	MOVV	R7, R6
	SC	R7, (R4)
	BEQ	R7, -4(PC)
	MOVW	R6, ret+16(FP)
	DBAR
	RET

TEXT ·Xadd64(SB), NOSPLIT, $0-24
	MOVV	ptr+0(FP), R4
	MOVV	delta+8(FP), R5
	DBAR
	LLV	(R4), R6
	ADDVU	R6, R5, R7
	MOVV	R7, R6
	SCV	R7, (R4)
	BEQ	R7, -4(PC)
	MOVV	R6, ret+16(FP)
	DBAR
	RET

TEXT ·Xchg(SB), NOSPLIT, $0-20
	MOVV	ptr+0(FP), R4
	MOVW	new+8(FP), R5

	DBAR
	MOVV	R5, R6

// uint64 Xadd64(uint64 volatile *ptr, int64 delta)
// Atomically:
//	*val += delta;
//	return *val;
TEXT ·Xadd64(SB), NOSPLIT, $0-24
	MOVV	ptr+0(FP), R2
	MOVV	delta+8(FP), R3
	SYNC
	LLV	(R2), R1
	ADDVU	R1, R3, R4
	MOVV	R4, R1
	SCV	R4, (R2)
	BEQ	R4, -4(PC)
	MOVV	R1, ret+16(FP)
	SYNC
	RET

// uint32 Xchg(ptr *uint32, new uint32)
// Atomically:
//	old := *ptr;
//	*ptr = new;

		readflags = regInfo{inputs: nil, outputs: []regMask{gp}}
	)
	ops := []opData{
		// binary ops
		{name: "ADDV", argLength: 2, reg: gp21, asm: "ADDVU", commutative: true},   // arg0 + arg1
		{name: "ADDVconst", argLength: 1, reg: gp11sp, asm: "ADDVU", aux: "Int64"}, // arg0 + auxInt. auxInt is 32-bit, also in other *const ops.
		{name: "SUBV", argLength: 2, reg: gp21, asm: "SUBVU"},                      // arg0 - arg1

		readflags = regInfo{inputs: nil, outputs: []regMask{gp}}
	)
	ops := []opData{
		// binary ops
		{name: "ADDV", argLength: 2, reg: gp21, asm: "ADDVU", commutative: true},                             // arg0 + arg1
		{name: "ADDVconst", argLength: 1, reg: gp11sp, asm: "ADDVU", aux: "Int64"},                           // arg0 + auxInt. auxInt is 32-bit, also in other *const ops.

	MOVV	$8(R29), R5		// arg 2 - tp
	MOVV	$87, R2			// sys_clock_gettime
	SYSCALL

	MOVV	8(R29), R3		// sec
	MOVV	16(R29), R5		// nsec

	MOVV	$1000000000, R4
	MULVU	R4, R3
	MOVV	LO, R3
	ADDVU	R5, R3
	MOVV	R3, ret+0(FP)
	RET

TEXT runtime·sigaction(SB),NOSPLIT,$0
	MOVW	sig+0(FP), R4		// arg 1 - signum
	MOVV	new+8(FP), R5		// arg 2 - new sigaction
	MOVV	old+16(FP), R6		// arg 3 - old sigaction