r12          uint32

	spr  uint32
	lrr  uint32
	pc   uint32
	cpsr uint32

	fpscr   uint32
	padding uint32

	floatNeon [16]neon128

	bvr      [8]uint32
	bcr      [8]uint32
	wvr      [1]uint32
	wcr      [1]uint32
	padding2 [2]uint32
}

func (c *context) ip() uintptr { return uintptr(c.pc) }
func (c *context) sp() uintptr { return uintptr(c.spr) }

		buf.WriteString(opcode[0:2])
		switch spr := inst.Args[0].(type) {
		case SpReg:
			switch spr {
			case 1:
				buf.WriteString("xer")
				startArg = 1
			case 8:
				buf.WriteString("lr")
				startArg = 1
			case 9:
				buf.WriteString("ctr")
				startArg = 1
			default:
				buf.WriteString("spr")
			}
		default:
			buf.WriteString("spr")
		}

	case "mfspr":

// This order should be strictly consistent to that in a.out.go
var cnames7 = []string{
	"", // C_NONE starts from 1
	"NONE",
	"REG",
	"ZREG",
	"RSP",
	"FREG",
	"VREG",
	"PAIR",
	"SHIFT",
	"EXTREG",
	"SPR",
	"SPOP",
	"COND",
	"ARNG",
	"ELEM",
	"LIST",
	"ZCON",
	"ABCON0",
	"ADDCON0",
	"ABCON",
	"AMCON",
	"ADDCON",
	"MBCON",
	"MOVCON",
	"BITCON",
	"ADDCON2",
	"LCON",
	"MOVCON2",

// license that can be found in the LICENSE file.

package ppc64

var cnames9 = []string{
	"NONE",
	"REGP",
	"REG",
	"FREGP",
	"FREG",
	"VREG",
	"VSREGP",
	"VSREG",
	"CREG",
	"CRBIT",
	"SPR",
	"MREG",
	"ZCON",
	"U1CON",
	"U2CON",
	"U3CON",
	"U4CON",
	"U5CON",
	"U8CON",
	"U15CON",
	"S16CON",
	"U16CON",
	"16CON",
	"U31CON",
	"S32CON",
	"U32CON",
	"32CON",
	"S34CON",

			return ppc64.REG_V0 + n, true
		}
	case "F":
		if 0 <= n && n <= 31 {
			return ppc64.REG_F0 + n, true
		}
	case "R":
		if 0 <= n && n <= 31 {
			return ppc64.REG_R0 + n, true
		}
	case "SPR":
		if 0 <= n && n <= 1024 {
			return ppc64.REG_SPR0 + n, true
		}
	}
	return 0, false

	{"R27", "R27"},
	{"R28", "R28"},
	{"R29", "R29"},
	{"R3", "R3"},
	{"R31", "R31"},
	{"R4", "R4"},
	{"R5", "R5"},
	{"R6", "R6"},
	{"R7", "R7"},
	{"R8", "R8"},
	{"R9", "R9"},
	{"SPR(269)", "SPR(269)"},
	{"a(FP)", "a(FP)"},
	{"g", "g"},
	{"ret+8(FP)", "ret+8(FP)"},
	{"runtime·abort(SB)", "runtime.abort(SB)"},
	{"·AddUint32(SB)", "pkg.AddUint32(SB)"},
	{"·trunc(SB)", "pkg.trunc(SB)"},

	BC $16,CR0LT,0(PC)              // 42000000
	BCL $16,CR0LT,0(PC)             // 42000001
	BC $18,CR0LT,0(PC)              // 42400000

	MOVD SPR(3), 4(R1)              // 7fe302a6fbe10004
	MOVD XER, 4(R1)                 // 7fe102a6fbe10004
	MOVD 4(R1), SPR(3)              // ebe100047fe303a6
	MOVD 4(R1), XER                 // ebe100047fe103a6
	OR $0, R0, R0                   // 60000000

		if p.To.Reg == 0 {
			c.ctxt.Diag("must specify FPSCR(n)\n%v", p)
		}
		o1 = OP_MTFSFI | (uint32(p.To.Reg)&15)<<23 | (uint32(c.regoff(&p.From))&31)<<12

	case 66: /* mov spr,r1; mov r1,spr */
		var r int
		var v int32
		if REG_R0 <= p.From.Reg && p.From.Reg <= REG_R31 {
			r = int(p.From.Reg)
			v = int32(p.To.Reg)
			o1 = OPVCC(31, 467, 0, 0) /* mtspr */
		} else {

	// ARM64 only.
	if p.arch.Family != sys.ARM64 {
		return false
	}
	// R1.xxx
	return p.peek() == '.'
}

// registerReference parses a register given either the name, R10, or a parenthesized form, SPR(10).
func (p *Parser) registerReference(name string) (int16, bool) {
	r, present := p.arch.Register[name]
	if present {
		return r, true
	}
	if !p.arch.RegisterPrefix[name] {

	MOVD	R4, LR
	RET

TEXT runtime·abort(SB),NOSPLIT|NOFRAME,$0-0
	MOVW	(R0), R0
	UNDEF

#define	TBR	268

// int64 runtime·cputicks(void)
TEXT runtime·cputicks(SB),NOSPLIT,$0-8
	MOVD	SPR(TBR), R3
	MOVD	R3, ret+0(FP)
	RET

// spillArgs stores return values from registers to a *internal/abi.RegArgs in R20.
TEXT runtime·spillArgs(SB),NOSPLIT,$0-0
	MOVD    R3, 0(R20)
	MOVD    R4, 8(R20)