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Results 1 - 10 of 13 for FMSUBD (0.19 sec)

  1. test/codegen/floats.go

    	// riscv64:"FMADDD\t"
    	return x*y + z
    }
    
    func FusedSub64_a(x, y, z float64) float64 {
    	// s390x:"FMSUB\t"
    	// ppc64x:"FMSUB\t"
    	// riscv64:"FMSUBD\t"
    	return x*y - z
    }
    
    func FusedSub64_b(x, y, z float64) float64 {
    	// arm64:"FMSUBD"
    	// riscv64:"FNMSUBD\t"
    	return z - x*y
    }
    
    func Cmp(f float64) bool {
    	// arm64:"FCMPD","(BGT|BLE|BMI|BPL)",-"CSET\tGT",-"CBZ"
    	return f > 4 || f < -4
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Thu Apr 04 15:24:29 UTC 2024
    - 4.9K bytes
    - Viewed (0)
  2. src/cmd/internal/obj/riscv/anames.go

    	"FMVXW",
    	"FMVWX",
    	"FEQS",
    	"FLTS",
    	"FLES",
    	"FCLASSS",
    	"FLD",
    	"FSD",
    	"FADDD",
    	"FSUBD",
    	"FMULD",
    	"FDIVD",
    	"FMIND",
    	"FMAXD",
    	"FSQRTD",
    	"FMADDD",
    	"FMSUBD",
    	"FNMADDD",
    	"FNMSUBD",
    	"FCVTWD",
    	"FCVTLD",
    	"FCVTDW",
    	"FCVTDL",
    	"FCVTWUD",
    	"FCVTLUD",
    	"FCVTDWU",
    	"FCVTDLU",
    	"FCVTSD",
    	"FCVTDS",
    	"FSGNJD",
    	"FSGNJND",
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Wed Mar 20 14:19:33 UTC 2024
    - 2.9K bytes
    - Viewed (0)
  3. test/codegen/math.go

    	// arm/6:"FMULAD"
    	// arm64:"FMADDD"
    	// s390x:"FMADD"
    	// ppc64x:"FMADD"
    	// riscv64:"FMADDD"
    	return math.FMA(x, y, z)
    }
    
    func fms(x, y, z float64) float64 {
    	// riscv64:"FMSUBD"
    	return math.FMA(x, y, -z)
    }
    
    func fnms(x, y, z float64) float64 {
    	// riscv64:"FNMSUBD",-"FNMADDD"
    	return math.FMA(-x, y, z)
    }
    
    func fnma(x, y, z float64) float64 {
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Thu Apr 04 15:24:29 UTC 2024
    - 6.2K bytes
    - Viewed (0)
  4. src/cmd/internal/obj/arm64/doc.go

    Examples:
    
    	MADD R2, R30, R22, R6       <=>    madd x6, x22, x2, x30
    	SMSUBL R10, R3, R17, R27    <=>    smsubl x27, w17, w10, x3
    
    (3) FMADDD, FMADDS, FMSUBD, FMSUBS, FNMADDD, FNMADDS, FNMSUBD, FNMSUBS <Fm>, <Fa>, <Fn>, <Fd>
    
    Examples:
    
    	FMADDD F30, F20, F3, F29    <=>    fmadd d29, d3, d30, d20
    	FNMSUBS F7, F25, F7, F22    <=>    fnmsub s22, s7, s7, s25
    
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Mon Aug 07 00:21:42 UTC 2023
    - 9.6K bytes
    - Viewed (0)
  5. src/cmd/compile/internal/ssa/_gen/RISCV64Ops.go

    		{name: "FMADDD", argLength: 3, reg: fp31, asm: "FMADDD", commutative: true, typ: "Float64"},                                         // (arg0 * arg1) + arg2
    		{name: "FMSUBD", argLength: 3, reg: fp31, asm: "FMSUBD", commutative: true, typ: "Float64"},                                         // (arg0 * arg1) - arg2
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Thu Mar 07 14:57:07 UTC 2024
    - 30.7K bytes
    - Viewed (0)
  6. src/cmd/asm/internal/asm/testdata/riscv64.s

    	FSGNJD	F1, F0, F2				// 53011022
    	FSGNJND	F1, F0, F2				// 53111022
    	FSGNJXD	F1, F0, F2				// 53211022
    	FMVXD	F0, X5					// d30200e2
    	FMVDX	X5, F0					// 538002f2
    	FMADDD	F1, F2, F3, F4				// 4382201a
    	FMSUBD	F1, F2, F3, F4				// 4782201a
    	FNMSUBD	F1, F2, F3, F4				// 4b82201a
    	FNMADDD	F1, F2, F3, F4				// 4f82201a
    
    	// 12.6: Double-Precision Floating-Point Classify Instruction
    	FCLASSD	F0, X5					// d31200e2
    
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Fri Mar 22 04:42:21 UTC 2024
    - 16.7K bytes
    - Viewed (0)
  7. src/cmd/compile/internal/ssa/_gen/ARM64Ops.go

    		{name: "FNMADDD", argLength: 3, reg: fp31, asm: "FNMADDD"}, // -arg0 - (arg1 * arg2)
    		{name: "FMSUBS", argLength: 3, reg: fp31, asm: "FMSUBS"},   // +arg0 - (arg1 * arg2)
    		{name: "FMSUBD", argLength: 3, reg: fp31, asm: "FMSUBD"},   // +arg0 - (arg1 * arg2)
    		{name: "FNMSUBS", argLength: 3, reg: fp31, asm: "FNMSUBS"}, // -arg0 + (arg1 * arg2)
    		{name: "FNMSUBD", argLength: 3, reg: fp31, asm: "FNMSUBD"}, // -arg0 + (arg1 * arg2)
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Thu May 23 15:49:20 UTC 2024
    - 58.8K bytes
    - Viewed (0)
  8. src/cmd/asm/internal/asm/testdata/arm64enc.s

    	FMOVD F2, F9                               // 4940601e
    	FMOVS F4, F27                              // 9b40201e
    	//TODO VFMOV $3.125, V8.D2                 // 28f5006f
    	FMSUBS F13, F21, F13, F19                  // b3d50d1f
    	FMSUBD F11, F7, F15, F31                   // ff9d4b1f
    	//TODO VFMUL V9.S[2], F21, F19             // b39a895f
    	//TODO VFMUL V26.S[2], V26.S2, V2.S2       // 429b9a0f
    	//TODO VFMUL V21.D2, V17.D2, V25.D2        // 39de756e
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Mon Jul 24 01:11:41 UTC 2023
    - 43.9K bytes
    - Viewed (0)
  9. src/cmd/compile/internal/ssa/rewriteRISCV64.go

    				continue
    			}
    			v.reset(OpRISCV64FNMSUBD)
    			v.AddArg3(x, y, z)
    			return true
    		}
    		break
    	}
    	// match: (FMADDD x y neg:(FNEGD z))
    	// cond: neg.Uses == 1
    	// result: (FMSUBD x y z)
    	for {
    		x := v_0
    		y := v_1
    		neg := v_2
    		if neg.Op != OpRISCV64FNEGD {
    			break
    		}
    		z := neg.Args[0]
    		if !(neg.Uses == 1) {
    			break
    		}
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Thu Mar 07 14:57:07 UTC 2024
    - 205.1K bytes
    - Viewed (0)
  10. src/cmd/compile/internal/ssa/_gen/ARM64.rules

    (FSUBD a (FMULD  x y)) && a.Block.Func.useFMA(v) => (FMSUBD  a x y)
    (FSUBS (FMULS  x y) a) && a.Block.Func.useFMA(v) => (FNMSUBS a x y)
    (FSUBD (FMULD  x y) a) && a.Block.Func.useFMA(v) => (FNMSUBD a x y)
    (FADDS a (FNMULS x y)) && a.Block.Func.useFMA(v) => (FMSUBS  a x y)
    (FADDD a (FNMULD x y)) && a.Block.Func.useFMA(v) => (FMSUBD  a x y)
    (FSUBS a (FNMULS x y)) && a.Block.Func.useFMA(v) => (FMADDS  a x y)
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Thu May 23 15:49:20 UTC 2024
    - 113.1K bytes
    - Viewed (0)
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