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Results 1 - 10 of 10 for Sub (0.13 sec)

  1. src/cmd/asm/internal/asm/testdata/mips64.s

    //	LSUBW rreg ',' sreg ',' rreg
    //	{
    //		outcode(int($1), &$2, int($4), &$6);
    //	}
    	SUB	R6, R26, R27	// 0346d822
    	SUBU	R6, R26, R27	// 0346d823
    	SUBV	R16, R17, R26	// 0230d02e
    	SUBVU	R16, R17, R26	// 0230d02f
    
    //	LSUBW imm ',' sreg ',' rreg
    //	{
    //		outcode(int($1), &$2, int($4), &$6);
    //	}
    	SUB	$-3126, R17, R22	// 22360c36
    	SUB	$3126, R17, R22		// 2236f3ca
    	SUBU	$16384, R17, R12	// 262cc000
    Others
    - Registered: Tue Apr 30 11:13:12 GMT 2024
    - Last Modified: Tue Aug 08 12:17:12 GMT 2023
    - 12.4K bytes
    - Viewed (0)
  2. src/cmd/asm/internal/asm/testdata/s390x.s

    	ADDW	R1, R2, R3            // b9f81032
    	ADDW	$8192, R1             // a71a2000
    	ADDW	$8192, R1, R2         // ec21200000d8
    	ADDE	R1, R2                // b9880021
    	SUB	R3, R4                // b9090043
    	SUB	R3, R4, R5            // b9e93054
    	SUB	$8192, R3             // a73be000
    	SUB	$8192, R3, R4         // ec43e00000d9
    	SUBC	R1, R2                // b90b0021
    	SUBC	$1, R1, R2            // ec21ffff00db
    	SUBC	R2, R3, R4            // b9eb2043
    Others
    - Registered: Tue Apr 30 11:13:12 GMT 2024
    - Last Modified: Wed Nov 22 03:55:32 GMT 2023
    - 21.6K bytes
    - Viewed (0)
  3. src/cmd/asm/internal/asm/testdata/arm.s

    	SUB	R0->28, R1           // 401e41e0
    	SUB	R0@>28, R1           // 601e41e0
    	SUB.S	R0<<28, R1           // 001e51e0
    	SUB.S	R0>>28, R1           // 201e51e0
    	SUB.S	R0->28, R1           // 401e51e0
    	SUB.S	R0@>28, R1           // 601e51e0
    	SUB	R0<<R1, R2, R3       // 103142e0
    	SUB	R0>>R1, R2, R3       // 303142e0
    	SUB	R0->R1, R2, R3       // 503142e0
    	SUB	R0@>R1, R2, R3       // 703142e0
    Others
    - Registered: Tue Apr 30 11:13:12 GMT 2024
    - Last Modified: Fri Dec 15 20:51:01 GMT 2023
    - 69K bytes
    - Viewed (0)
  4. src/cmd/asm/internal/asm/testdata/arm64.s

    	SUB	$0x000aaa, R2, R3               // SUB $2730, R2, R3                      // 43a82ad1
    	SUB	$0x000aaa, R2                   // SUB $2730, R2                          // 42a82ad1
    	SUB	$0xaaa000, R2, R3               // SUB $11182080, R2, R3                  // 43a86ad1
    	SUB	$0xaaa000, R2                   // SUB $11182080, R2                      // 42a86ad1
    Others
    - Registered: Tue Apr 30 11:13:12 GMT 2024
    - Last Modified: Fri Dec 08 03:28:17 GMT 2023
    - 94.9K bytes
    - Viewed (0)
  5. src/cmd/asm/internal/asm/testdata/arm64enc.s

    	SUBW R20.UXTW<<2, R23, R19                 // f34a344b
    	SUB R5.SXTW<<2, R1, R26                    // 3ac825cb
    	SUB $(1923<<12), R4, R27                   // SUB $7876608, R4, R27         // 9b0c5ed1
    	SUBW $(1923<<12), R4, R27                  // SUBW $7876608, R4, R27        // 9b0c5e51
    	SUBW R12<<29, R7, R8                       // e8740c4b
    	SUB R12<<61, R7, R8                        // e8f40ccb
    Others
    - Registered: Tue Apr 30 11:13:12 GMT 2024
    - Last Modified: Mon Jul 24 01:11:41 GMT 2023
    - 43.9K bytes
    - Viewed (1)
  6. src/cmd/asm/internal/asm/testdata/ppc64.s

    	EQV R3, R4, R5                  // 7c851a38
    	EQVCC R3, R4, R5                // 7c851a39
    	NOR R3, R4, R5                  // 7c8518f8
    	NORCC R3, R4, R5                // 7c8518f9
    
    	SUB R3, R4                      // 7c832050
    	SUB R3, R4, R5                  // 7ca32050
    	SUBC R3, R4                     // 7c832010
    	SUBC R3, R4, R5                 // 7ca32010
    	SUBCC R3, R4, R5                // 7ca32051
    Others
    - Registered: Tue Apr 30 11:13:12 GMT 2024
    - Last Modified: Wed Apr 24 15:53:25 GMT 2024
    - 49K bytes
    - Viewed (0)
  7. src/cmd/asm/internal/asm/testdata/riscv64.s

    	SRL	X6, X5, X7				// b3d36200
    	SRL	X5, X6					// 33535300
    	SRL	$1, X5, X6				// 13d31200
    	SRL	$1, X5					// 93d21200
    
    	SUB	X6, X5, X7				// b3836240
    	SUB	X5, X6					// 33035340
    	SUB	$-2047, X5, X6				// 1383f27f
    	SUB	$2048, X5, X6				// 13830280
    	SUB	$-2047, X5				// 9382f27f
    	SUB	$2048, X5				// 93820280
    
    	SRA	X6, X5, X7				// b3d36240
    	SRA	X5, X6					// 33535340
    	SRA	$1, X5, X6				// 13d31240
    Others
    - Registered: Tue Apr 30 11:13:12 GMT 2024
    - Last Modified: Fri Mar 22 04:42:21 GMT 2024
    - 16.7K bytes
    - Viewed (1)
  8. src/cmd/asm/internal/asm/testdata/loong64enc1.s

    	MOVV	$65536, R4		// 04020014
    	MOVV	$4096, R4		// 24000014
    	MOVW	R4, R5			// 85001700
    	MOVV	R4, R5			// 85001500
    	MOVBU	R4, R5			// 85fc4303
    	SUB	R4, R5, R6		// a6101100
    	SUBV	R4, R5, R6		// a6901100
    	ADD	R4, R5, R6		// a6101000
    	ADDV	R4, R5, R6		// a6901000
    	AND	R4, R5, R6		// a6901400
    	SUB	R4, R5			// a5101100
    	SUBV	R4, R5			// a5901100
    	ADD	R4, R5			// a5101000
    	ADDV	R4, R5			// a5901000
    	AND	R4, R5			// a5901400
    Others
    - Registered: Tue Apr 30 11:13:12 GMT 2024
    - Last Modified: Fri Mar 31 02:56:19 GMT 2023
    - 6.4K bytes
    - Viewed (0)
  9. src/cmd/asm/internal/asm/testdata/armerror.s

    	MOVF	F2, 0x00ffffff(F2) // ERROR "illegal base register"
    	MOVD	F2, 0x00ffffff(F2) // ERROR "illegal base register"
    	MULS.S	R1, R2, R3, R4     // ERROR "invalid .S suffix"
    	ADD.P	R1, R2, R3         // ERROR "invalid .P suffix"
    	SUB.W	R2, R3             // ERROR "invalid .W suffix"
    	BL	4(R4)              // ERROR "non-zero offset"
    	ADDF	F0, R1, F2         // ERROR "illegal combination"
    	SWI	(R0)               // ERROR "illegal combination"
    Others
    - Registered: Tue Apr 30 11:13:12 GMT 2024
    - Last Modified: Fri Nov 03 14:06:21 GMT 2017
    - 14.4K bytes
    - Viewed (0)
  10. src/cmd/asm/internal/asm/testdata/arm64error.s

    	ADDS	R7@>2, R5, R16                                   // ERROR "unsupported shift operator"
    	ADDSW	R7@>2, R5, R16                                   // ERROR "unsupported shift operator"
    	SUB	R7@>2, R5, R16                                   // ERROR "unsupported shift operator"
    	SUBW	R7@>2, R5, R16                                   // ERROR "unsupported shift operator"
    Others
    - Registered: Tue Apr 30 11:13:12 GMT 2024
    - Last Modified: Fri Dec 08 03:28:17 GMT 2023
    - 37.8K bytes
    - Viewed (0)
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