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Results 1 - 7 of 7 for vsrad (0.36 sec)
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src/cmd/internal/obj/ppc64/a.out.go
ARLDCL ARLDCLCC ARLDICL ARLDICLCC ARLDIC ARLDICCC ACLRLSLDI AROTL AROTLW ASLBIA ASLBIE ASLBMFEE ASLBMFEV ASLBMTE ASLD ASLDCC ASRD ASRAD ASRADCC ASRDCC AEXTSWSLI AEXTSWSLICC ASTDCCC ATD ASETB /* 64-bit pseudo operation */ ADWORD AREMD AREMDU /* more 64-bit operations */ AHRFID APOPCNTD
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon Apr 01 18:50:29 UTC 2024 - 16K bytes - Viewed (0) -
test/codegen/arithmetic.go
// arm64:"TST\t[$]63",-"UDIV",-"ASR",-"AND" // ppc64x:"ANDCC",-"RLDICL",-"SRAD",-"CMP" a := n1%64 == 0 // signed divisible // 386:"TESTL\t[$]63",-"DIVL",-"SHRL" // amd64:"TESTQ\t[$]63",-"DIVQ",-"SHRQ" // arm:"AND\t[$]63",-".*udiv",-"SRA" // arm64:"TST\t[$]63",-"UDIV",-"ASR",-"AND" // ppc64x:"ANDCC",-"RLDICL",-"SRAD",-"CMP" b := n2%64 != 0 // signed indivisible return a, b }
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri May 17 15:28:00 UTC 2024 - 15.2K bytes - Viewed (0) -
test/codegen/shift.go
return uint64(v) >> 16 } func rshConst64Ux64Overflow8(v uint8) uint64 { // riscv64:"MOV\t\\$0,",-"SRL" return uint64(v) >> 8 } func rshConst64x64(v int64) int64 { // ppc64x:"SRAD" // riscv64:"SRAI\t",-"OR",-"SLTIU" return v >> uint64(33) } func rshConst64x64Overflow32(v int32) int64 { // riscv64:"SRAIW",-"SLLI",-"SRAI\t" return int64(v) >> 32 }
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue May 21 18:53:43 UTC 2024 - 12.7K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/PPC64Ops.go
{name: "FMSUB", argLength: 3, reg: fp31, asm: "FMSUB"}, // arg0*arg1 - arg2 {name: "FMSUBS", argLength: 3, reg: fp31, asm: "FMSUBS"}, // arg0*arg1 - arg2 {name: "SRAD", argLength: 2, reg: gp21cxer, asm: "SRAD"}, // signed arg0 >> (arg1&127), 64 bit width (note: 127, not 63!) {name: "SRAW", argLength: 2, reg: gp21cxer, asm: "SRAW"}, // signed arg0 >> (arg1&63), 32 bit width
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed May 22 19:59:38 UTC 2024 - 43.8K bytes - Viewed (0) -
src/hash/crc32/crc32_ppc64le.s
CMP $0,R6 // len == 0? BNE start MOVW R3,ret+40(FP) // return crc RET start: NOR R3,R3,R7 // ^crc MOVWZ R7,R7 // 32 bits CMP R6,$16 MOVD R6,CTR BLT short SRAD $3,R6,R8 // 8 byte chunks MOVD R8,CTR loop: MOVWZ 0(R5),R8 // 0-3 bytes of p ?Endian? MOVWZ 4(R5),R9 // 4-7 bytes of p MOVD R4,R10 // &tab[0] XOR R7,R8,R7 // crc ^= byte[0:3]
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon May 06 12:09:50 UTC 2024 - 13.1K bytes - Viewed (0) -
src/math/big/arith_ppc64x.s
ADD $-2, R4, R16 PCALIGN $16 loopback: ADD $-1, R8, R10 SLD $3, R10 LXVD2X (R6)(R10), VS32 // load x[i-1], x[i] SLD $3, R8, R12 LXVD2X (R6)(R12), VS33 // load x[i], x[i+1] VSRD V0, V4, V3 // x[i-1]>>s, x[i]>>s VSLD V1, V2, V5 // x[i]<<ŝ, x[i+1]<<ŝ VOR V3, V5, V5 // Or(|) the two registers together STXVD2X VS37, (R3)(R10) // store into z[i-1] and z[i]
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed May 22 18:17:17 UTC 2024 - 16.8K bytes - Viewed (0) -
src/crypto/aes/gcm_ppc64x.s
VADDUBM XC2, XC2, XC2 // 0xc2... VSPLTISB $7, T2 VOR XC2, T1, XC2 // 0xc2....01 VSPLTB $0, H, T1 // most significant byte VSL H, T0, H // H<<=1 VSRAB T1, T2, T1 // broadcast carry bit VAND T1, XC2, T1 VXOR H, T1, IN // twisted H VSLDOI $8, IN, IN, H // twist even more ... VSLDOI $8, ZERO, XC2, XC2 // 0xc2.0
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon Mar 04 17:29:44 UTC 2024 - 27.1K bytes - Viewed (0)