Search Options

Results per page
Sort
Preferred Languages
Advance

Results 1 - 7 of 7 for aesRnd (0.18 sec)

  1. src/crypto/aes/asm_amd64.s

    	JE Lenc192
    	JB Lenc128
    Lenc256:
    	MOVUPS 0(AX), X1
    	AESENC X1, X0
    	MOVUPS 16(AX), X1
    	AESENC X1, X0
    	ADDQ $32, AX
    Lenc192:
    	MOVUPS 0(AX), X1
    	AESENC X1, X0
    	MOVUPS 16(AX), X1
    	AESENC X1, X0
    	ADDQ $32, AX
    Lenc128:
    	MOVUPS 0(AX), X1
    	AESENC X1, X0
    	MOVUPS 16(AX), X1
    	AESENC X1, X0
    	MOVUPS 32(AX), X1
    	AESENC X1, X0
    	MOVUPS 48(AX), X1
    	AESENC X1, X0
    	MOVUPS 64(AX), X1
    	AESENC X1, X0
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Mon Mar 04 17:29:44 UTC 2024
    - 5.4K bytes
    - Viewed (0)
  2. src/crypto/aes/asm_arm64.s

    	VLD1.P	48(R10), [V13.B16, V14.B16, V15.B16]
    	AESD	V5.B16, V0.B16
    	AESIMC	V0.B16, V0.B16
    	AESD	V6.B16, V0.B16
    	AESIMC	V0.B16, V0.B16
    	AESD	V7.B16, V0.B16
    	AESIMC	V0.B16, V0.B16
    	AESD	V8.B16, V0.B16
    	AESIMC	V0.B16, V0.B16
    	AESD	V9.B16, V0.B16
    	AESIMC	V0.B16, V0.B16
    	AESD	V10.B16, V0.B16
    	AESIMC	V0.B16, V0.B16
    	AESD	V11.B16, V0.B16
    	AESIMC	V0.B16, V0.B16
    	AESD	V12.B16, V0.B16
    	AESIMC	V0.B16, V0.B16
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Mon Mar 04 17:29:44 UTC 2024
    - 6.9K bytes
    - Viewed (0)
  3. src/cmd/trace/jsontrace.go

    		}
    		if a.Start != b.Start {
    			return cmp.Compare(aStart, bStart)
    		}
    		// Break ties with the end time.
    		aEnd, bEnd := parsed.endTime(), parsed.endTime()
    		if a.End != nil {
    			aEnd = a.End.Time()
    		}
    		if b.End != nil {
    			bEnd = b.End.Time()
    		}
    		return cmp.Compare(aEnd, bEnd)
    	})
    }
    
    func defaultGenOpts() *genOpts {
    	return &genOpts{
    		startTime: time.Duration(0),
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Fri May 17 18:48:18 UTC 2024
    - 6.5K bytes
    - Viewed (0)
  4. src/cmd/internal/obj/wasm/a.out.go

    	// Their order matters, since it matches the opcode encoding.
    	// Gaps in the encoding are indicated by comments.
    
    	AUnreachable // opcode 0x00
    	ANop
    	ABlock
    	ALoop
    	AIf
    	AElse
    
    	AEnd // opcode 0x0B
    	ABr
    	ABrIf
    	ABrTable
    	// ACall and AReturn are WebAssembly instructions. obj.ACALL and obj.ARET are higher level instructions
    	// with Go semantics, e.g. they manipulate the Go stack on the linear memory.
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Thu Mar 02 05:28:55 UTC 2023
    - 4.3K bytes
    - Viewed (0)
  5. src/cmd/internal/obj/arm64/anames.go

    package arm64
    
    import "cmd/internal/obj"
    
    var Anames = []string{
    	obj.A_ARCHSPECIFIC: "ADC",
    	"ADCS",
    	"ADCSW",
    	"ADCW",
    	"ADD",
    	"ADDS",
    	"ADDSW",
    	"ADDW",
    	"ADR",
    	"ADRP",
    	"AESD",
    	"AESE",
    	"AESIMC",
    	"AESMC",
    	"AND",
    	"ANDS",
    	"ANDSW",
    	"ANDW",
    	"ASR",
    	"ASRW",
    	"AT",
    	"BCC",
    	"BCS",
    	"BEQ",
    	"BFI",
    	"BFIW",
    	"BFM",
    	"BFMW",
    	"BFXIL",
    	"BFXILW",
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Thu May 18 01:40:37 UTC 2023
    - 5.4K bytes
    - Viewed (0)
  6. src/cmd/internal/obj/arm64/doc.go

    	VADD V5.H8, V18.H8, V9.H8         <=>      add v9.8h, v18.8h, v5.8h
    	VLD1.P (R6)(R11), [V31.D1]        <=>      ld1 {v31.1d}, [x6], x11
    	VFMLA V29.S2, V20.S2, V14.S2      <=>      fmla v14.2s, v20.2s, v29.2s
    	AESD V22.B16, V19.B16             <=>      aesd v19.16b, v22.16b
    	SCVTFWS R3, F16                   <=>      scvtf s17, w6
    
    6. Align directive
    
    Go asm supports the PCALIGN directive, which indicates that the next instruction should be aligned
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Mon Aug 07 00:21:42 UTC 2023
    - 9.6K bytes
    - Viewed (0)
  7. src/internal/buildcfg/cfg.go

    	return
    }
    
    type Goarm64Features struct {
    	Version string
    	// Large Systems Extension
    	LSE bool
    	// ARM v8.0 Cryptographic Extension. It includes the following features:
    	// * FEAT_AES, which includes the AESD and AESE instructions.
    	// * FEAT_PMULL, which includes the PMULL, PMULL2 instructions.
    	// * FEAT_SHA1, which includes the SHA1* instructions.
    	// * FEAT_SHA256, which includes the SHA256* instructions.
    	Crypto bool
    }
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Thu Mar 21 20:08:06 UTC 2024
    - 9.5K bytes
    - Viewed (0)
Back to top