</goals>
          </execution>
        </executions>
        <configuration>
          <instructions>
            <Export-Package>com.google.common.util.concurrent.internal</Export-Package>
            <Bundle-DocURL>https://github.com/google/guava/</Bundle-DocURL>
          </instructions>
        </configuration>
      </plugin>
      <plugin>
        <artifactId>maven-javadoc-plugin</artifactId>

name: Bug Report
description: Create a report to help us improve
labels: [ "a:bug", "to-triage" ]
assignees: [ ]
body:
  - type: markdown
    attributes:
      value: |
        Please follow the instructions below.
        We receive dozens of issues every week, so to stay productive, we will close issues that don't provide enough information.

## Team

There's a team of people that help manage and maintain the project. 😎

They have different levels of permissions and [specific instructions](./management-tasks.md){.internal-link target=_blank}.

Some of the tasks they can perform include:

* Adding labels to PRs.
* Editing PR titles.
* Adding commits on top of PRs to tweak them.

	FTINTRNEVD	F0, F2		// 02e81a01

	// LDX.{B,BU,H,HU,W,WU,D} instructions
	MOVB		(R14)(R13), R12	// cc350038
	MOVBU		(R14)(R13), R12	// cc352038
	MOVH		(R14)(R13), R12	// cc350438
	MOVHU		(R14)(R13), R12	// cc352438
	MOVW		(R14)(R13), R12	// cc350838
	MOVWU		(R14)(R13), R12	// cc352838
	MOVV		(R14)(R13), R12	// cc350c38

	// STX.{B,H,W,D} instructions
	MOVB		R12, (R14)(R13)	// cc351038
	MOVH		R12, (R14)(R13)	// cc351438

	MOVW	R1, M1

	//	LMOVW mreg ',' rreg
	//	{
	//		outcode(int($1), &$2, 0, &$4);
	//	}
	MOVW	M1, R1
	MOVW	M1, R1


	//
	// integer operations
	// logical instructions
	// shift instructions
	// unary instructions
	//
	//	LADDW rreg ',' sreg ',' rreg
	//	{
	//		outcode(int($1), &$2, int($4), &$6);
	//	}
	ADD	R1, R2, R3

	//	LADDW imm ',' sreg ',' rreg
	//	{

			}
		} else if p.arch.Family == sys.Loong64 {
			if arch.IsLoong64RDTIME(op) {
				// The Loong64 RDTIME family of instructions is a bit special,
				// in that both its register operands are outputs
				prog.To = a[0]
				if a[1].Type != obj.TYPE_REG {
					p.errorf("invalid addressing modes for 2nd operand to %s instruction, must be register", op)
					return
				}
				prog.RegTo2 = a[1].Reg
				break
			}
		}

## Supported Versions

Information about supported Kubernetes versions can be found on the
[Kubernetes version and version skew support policy] page on the Kubernetes website.

## Reporting a Vulnerability

Instructions for reporting a vulnerability can be found on the
[Kubernetes Security and Disclosure Information] page.

// This file encapsulates some of the odd characteristics of the RISCV64
// instruction set, to minimize its interaction with the core of the
// assembler.

package arch

import (
	"cmd/internal/obj"
	"cmd/internal/obj/riscv"
)

// IsRISCV64AMO reports whether the op (as defined by a riscv.A*
// constant) is one of the AMO instructions that requires special
// handling.
func IsRISCV64AMO(op obj.As) bool {
	switch op {

# Security Policy

## Supported Versions

Information about supported Istio versions can be found on the
[Support Announcements] page on Istio's website.

## Reporting a Vulnerability

Instructions for reporting a vulnerability can be found on the
[Istio Security Vulnerabilities] page. The Istio Product Security Working Group receives
vulnerability and security issue reports, and the company affiliation of the members of

			</plugin>
			<plugin>
				<groupId>org.apache.felix</groupId>
				<artifactId>maven-bundle-plugin</artifactId>
				<version>5.1.9</version>
				<extensions>true</extensions>

				<configuration>
					<instructions>
						<Bundle-Version>${osgi.version}</Bundle-Version>
						<Bundle-License>LGPL</Bundle-License>
						<Bundle-Vendor>CodeLibs</Bundle-Vendor>
						<Bundle-SymbolicName>org.codelibs.jcifs</Bundle-SymbolicName>