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Results 11 - 20 of 25 for cmovz (0.06 sec)
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src/cmd/compile/internal/ssa/_gen/AMD64.rules
=> (CMOVWNE y x (CMPQconst [0] check)) // Absorb InvertFlags (CMOVQ(EQ|NE|LT|GT|LE|GE|HI|CS|CC|LS) x y (InvertFlags cond)) => (CMOVQ(EQ|NE|GT|LT|GE|LE|CS|HI|LS|CC) x y cond) (CMOVL(EQ|NE|LT|GT|LE|GE|HI|CS|CC|LS) x y (InvertFlags cond)) => (CMOVL(EQ|NE|GT|LT|GE|LE|CS|HI|LS|CC) x y cond) (CMOVW(EQ|NE|LT|GT|LE|GE|HI|CS|CC|LS) x y (InvertFlags cond)) => (CMOVW(EQ|NE|GT|LT|GE|LE|CS|HI|LS|CC) x y cond)
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Mar 12 19:38:41 UTC 2024 - 93.9K bytes - Viewed (0) -
src/cmd/internal/obj/arm64/a.out.go
C_BITCON // bitfield and logical immediate masks C_ADDCON2 // 24-bit constant C_LCON // 32-bit constant C_MOVCON2 // a constant that can be loaded with one MOVZ/MOVN and one MOVK C_MOVCON3 // a constant that can be loaded with one MOVZ/MOVN and two MOVKs C_VCON // 64-bit constant C_FCON // floating-point constant C_VCONADDR // 64-bit memory address C_AACON // ADDCON offset in auto constant $a(FP)
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed Oct 18 17:56:30 UTC 2023 - 18.1K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/branchelim.go
// amd64 doesn't support CMOV with byte registers return false } return true default: return false } } // elimIf converts the one-way branch starting at dom in f to a conditional move if possible. // loadAddr is a set of values which are used to compute the address of a load. // Those values are exempt from CMOV generation.
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed Nov 30 17:46:51 UTC 2022 - 12.7K bytes - Viewed (0) -
src/cmd/internal/obj/arm64/anames.go
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu May 18 01:40:37 UTC 2023 - 5.4K bytes - Viewed (0) -
src/cmd/internal/obj/arm64/doc.go
VMOVQ $0x1122334455667788, $0x99aabbccddeeff00, V2 // V2=0x99aabbccddeeff001122334455667788 8. Move an optionally-shifted 16-bit immediate value to a register. The instructions are MOVK(W), MOVZ(W) and MOVN(W), the assembly syntax is "op $(uimm16<<shift), <Rd>". The <uimm16> is the 16-bit unsigned immediate, in the range 0 to 65535; For the 32-bit variant, the <shift> is 0 or 16, for the
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon Aug 07 00:21:42 UTC 2023 - 9.6K bytes - Viewed (0) -
src/cmd/internal/obj/mips/a.out.go
AADDF AADDU AADDW AAND ABEQ ABFPF ABFPT ABGEZ ABGEZAL ABGTZ ABLEZ ABLTZ ABLTZAL ABNE ABREAK ACLO ACLZ ACMOVF ACMOVN ACMOVT ACMOVZ ACMPEQD ACMPEQF ACMPGED ACMPGEF ACMPGTD ACMPGTF ADIV ADIVD ADIVF ADIVU ADIVW AGOK ALL ALLV ALUI AMADD AMOVB AMOVBU AMOVD
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Aug 08 12:17:12 UTC 2023 - 7.6K bytes - Viewed (0) -
src/cmd/internal/obj/arm64/asm7.go
rel.Off = int32(c.pc) rel.Siz = 8 rel.Sym = p.From.Sym rel.Add = p.From.Offset rel.Type = objabi.R_ADDRARM64 case 69: /* LE model movd $tlsvar, reg -> movz reg, 0 + reloc */ o1 = c.opirr(p, AMOVZ) o1 |= uint32(p.To.Reg & 31) rel := obj.Addrel(c.cursym) rel.Off = int32(c.pc) rel.Siz = 4 rel.Sym = p.From.Sym rel.Type = objabi.R_ARM64_TLS_LE
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed May 15 15:44:14 UTC 2024 - 201.1K bytes - Viewed (0) -
src/cmd/vendor/golang.org/x/arch/arm64/arm64asm/tables.go
// MOVZ <Wd>, #<imm>{, LSL #<shift>} {0xff800000, 0x52800000, MOVZ, instArgs{arg_Wd, arg_immediate_OptLSL_amount_16_0_16}, nil}, // MOV <Xd>, #<imm> {0xff800000, 0xd2800000, MOV, instArgs{arg_Xd, arg_immediate_shift_64_implicit_imm16_hw}, mov_movz_64_movewide_cond}, // MOVZ <Xd>, #<imm>{, LSL #<shift>} {0xff800000, 0xd2800000, MOVZ, instArgs{arg_Xd, arg_immediate_OptLSL_amount_16_0_48}, nil},
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed Aug 16 17:57:48 UTC 2017 - 211.8K bytes - Viewed (0) -
src/cmd/link/internal/amd64/asm.go
writeableData[r.Off()-2] = 0x8d su.SetRelocType(rIdx, objabi.R_PCREL) su.SetRelocAdd(rIdx, r.Add()+4) return true } } // fall back to using GOT and hope for the best (CMOV*) // TODO: just needs relocation, no need to put in .dynsym ld.AddGotSym(target, ldr, syms, targ, uint32(elf.R_X86_64_GLOB_DAT)) su.SetRelocType(rIdx, objabi.R_PCREL) su.SetRelocSym(rIdx, syms.GOT)
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed Aug 23 05:58:20 UTC 2023 - 21K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/AMD64Ops.go
{name: "CMOVWCS", argLength: 3, reg: gp21, asm: "CMOVWCS", resultInArg0: true}, // CMOV with floating point instructions. We need separate pseudo-op to handle // InvertFlags correctly, and to generate special code that handles NaN (unordered flag). // NOTE: the fact that CMOV*EQF here is marked to generate CMOV*NE is not a bug. See // code generation in amd64/ssa.go.
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Aug 04 16:40:24 UTC 2023 - 98K bytes - Viewed (1)