||    conditional OR     p || q  is  "if p then true else q"
!     NOT                !p      is  "not p"
</pre>


<h3 id="Address_operators">Address operators</h3>

<p>
For an operand <code>x</code> of type <code>T</code>, the address operation
<code>&amp;x</code> generates a pointer of type <code>*T</code> to <code>x</code>.
The operand must be <i>addressable</i>,

	MOVL (AX)(Y0*1), AX             // ERROR "invalid instruction"
	// VSIB/VM is invalid without vector index.
	// TODO(quasilyte): improve error message (#21860).
	// "invalid VSIB address (missing vector index)"
	VPGATHERQQ Y2, (BP), Y1         // ERROR "invalid instruction"
	// AVX2GATHER mask/index/dest #UD cases.
	VPGATHERQQ Y2, (BP)(X2*2), Y2   // ERROR "mask, index, and destination registers should be distinct"

	if err != nil {
		p.errorf("bad size for DATA argument: %q", szop)
	}
	op = op[:n-2]
	nameAddr := p.address(op)
	if !p.validSymbol("DATA", &nameAddr, true) {
		return
	}
	name := symbolName(&nameAddr)

	// Operand 1 is an immediate constant or address.
	valueAddr := p.address(operands[1])
	switch valueAddr.Type {
	case obj.TYPE_CONST, obj.TYPE_FCONST, obj.TYPE_SCONST, obj.TYPE_ADDR:
		// OK

pkg debug/pe, const IMAGE_FILE_DLL ideal-int
pkg debug/pe, const IMAGE_FILE_EXECUTABLE_IMAGE = 2
pkg debug/pe, const IMAGE_FILE_EXECUTABLE_IMAGE ideal-int
pkg debug/pe, const IMAGE_FILE_LARGE_ADDRESS_AWARE = 32
pkg debug/pe, const IMAGE_FILE_LARGE_ADDRESS_AWARE ideal-int
pkg debug/pe, const IMAGE_FILE_LINE_NUMS_STRIPPED = 4
pkg debug/pe, const IMAGE_FILE_LINE_NUMS_STRIPPED ideal-int
pkg debug/pe, const IMAGE_FILE_LOCAL_SYMS_STRIPPED = 8

		symtab, err := f.Symbols()
		if err == nil {
			// Check for use of -fsanitize=hwaddress (issue 53285).
			removeTag := func(v uint64) uint64 { return v }
			if goarch == "arm64" {
				for i := range symtab {
					if symtab[i].Name == "__hwasan_init" {
						// -fsanitize=hwaddress on ARM
						// uses the upper byte of a
						// memory address as a hardware
						// tag. Remove it so that
						// we can find the associated

pkg net/mail, method (*Address) String() string
pkg net/mail, method (Header) AddressList(string) ([]*Address, error)
pkg net/mail, method (Header) Date() (time.Time, error)
pkg net/mail, method (Header) Get(string) string
pkg net/mail, type Address struct
pkg net/mail, type Address struct, Address string
pkg net/mail, type Address struct, Name string
pkg net/mail, type Header map[string][]string

	JMP	4(X5)					// 67804200

	// CALL and JMP to symbol are encoded as JAL (using LR or ZERO
	// respectively), with a R_RISCV_JAL relocation. The linker resolves
	// the real address and updates the immediate, using a trampoline in
	// the case where the address is not directly reachable.
	CALL	asmtest(SB)				// ef000000
	JMP	asmtest(SB)				// 6f000000

	// Branch pseudo-instructions
	BEQZ	X5, 2(PC)				// 63840200

	FMOVD	0x1006ff8(R1), F2	// FMOVD	16805880(R1), F2	// 3bfc7f9162ff7ffd

// very large or unaligned offset uses constant pool.
// the encoding cannot be checked as the address of the constant pool is unknown.
// here we only test that they can be assembled.
	MOVB	R1, 0x1000000(R2)	// MOVB		R1, 16777216(R2)
	MOVB	R1, 0x44332211(R2)	// MOVB		R1, 1144201745(R2)

		case "UXTH":
			if a.Type == obj.TYPE_MEM {
				return errors.New("invalid shift for the register offset addressing mode")
			}
			a.Reg = arm64.REG_UXTH + Rnum
		case "UXTW":
			// effective address of memory is a base register value and an offset register value.
			if a.Type == obj.TYPE_MEM {
				a.Index = arm64.REG_UXTW + Rnum
			} else {
				a.Reg = arm64.REG_UXTW + Rnum
			}
		case "UXTX":

pkg debug/elf, const DT_GNU_PRELINKED DynTag
pkg debug/elf, const DT_MIPS_AUX_DYNAMIC = 1879048241
pkg debug/elf, const DT_MIPS_AUX_DYNAMIC DynTag
pkg debug/elf, const DT_MIPS_BASE_ADDRESS = 1879048198
pkg debug/elf, const DT_MIPS_BASE_ADDRESS DynTag
pkg debug/elf, const DT_MIPS_COMPACT_SIZE = 1879048239
pkg debug/elf, const DT_MIPS_COMPACT_SIZE DynTag
pkg debug/elf, const DT_MIPS_CONFLICT = 1879048200