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Results 61 - 69 of 69 for r31 (0.2 sec)
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src/cmd/internal/obj/ppc64/a.out.go
* powerpc 64 */ const ( NSNAME = 8 NSYM = 50 NREG = 32 /* number of general registers */ NFREG = 32 /* number of floating point registers */ ) const ( /* RBasePPC64 = 4096 */ /* R0=4096 ... R31=4127 */ REG_R0 = obj.RBasePPC64 + iota REG_R1 REG_R2 REG_R3 REG_R4 REG_R5 REG_R6 REG_R7 REG_R8 REG_R9 REG_R10 REG_R11 REG_R12 REG_R13 REG_R14 REG_R15 REG_R16
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon Apr 01 18:50:29 UTC 2024 - 16K bytes - Viewed (0) -
src/cmd/internal/obj/arm64/a.out.go
REGMAX = REG_R25 REGCTXT = REG_R26 // environment for closures REGTMP = REG_R27 // reserved for liblink REGG = REG_R28 // G REGFP = REG_R29 // frame pointer REGLINK = REG_R30 // ARM64 uses R31 as both stack pointer and zero register, // depending on the instruction. To differentiate RSP from ZR, // we use a different numeric value for REGZERO and REGSP. REGZERO = REG_R31 REGSP = REG_RSP
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed Oct 18 17:56:30 UTC 2023 - 18.1K bytes - Viewed (0) -
src/cmd/internal/obj/loong64/obj.go
// q1: BNE R20, done p = obj.Appendp(p, c.newprog) q1 := p p.As = ABNE p.From.Type = obj.TYPE_REG p.From.Reg = REG_R20 p.To.Type = obj.TYPE_BRANCH p.Mark |= BRANCH // MOV LINK, R31 p = obj.Appendp(p, c.newprog) p.As = mov p.From.Type = obj.TYPE_REG p.From.Reg = REGLINK p.To.Type = obj.TYPE_REG p.To.Reg = REG_R31 if q != nil { q.To.SetTarget(p) p.Mark |= LABEL
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Nov 21 19:22:18 UTC 2023 - 19.7K bytes - Viewed (0) -
src/cmd/link/internal/ppc64/asm.go
r, _ := tramp.AddRel(objabi.R_ADDRPOWER) if r2Valid(ctxt) { // Use a TOC relative address if R2 holds the TOC pointer o1 |= uint32(2 << 16) // Transform lis r31,ha into addis r31,r2,ha r.SetType(objabi.R_ADDRPOWER_TOCREL) } r.SetOff(0) r.SetSiz(8) // generates 2 relocations: HA + LO r.SetSym(target) r.SetAdd(offset) } else {
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Mar 19 20:54:08 UTC 2024 - 63.7K bytes - Viewed (0) -
src/cmd/internal/obj/ppc64/obj9.go
// the frame size is too large. The link register must be saved // even for non-empty leaf functions so that traceback works. if autosize >= -BIG && autosize <= BIG { // Use MOVDU to adjust R1 when saving R31, if autosize is small. q = obj.Appendp(q, c.newprog) q.As = AMOVD q.Pos = p.Pos q.From.Type = obj.TYPE_REG q.From.Reg = REG_LR q.To.Type = obj.TYPE_REG q.To.Reg = REGTMP
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed May 22 18:17:17 UTC 2024 - 40.8K bytes - Viewed (0) -
doc/asm.html
It is a scaled mode as on the x86, but the only scale allowed is <code>1</code>. </li> </ul> <h3 id="mips">MIPS, MIPS64</h3> <p> General purpose registers are named <code>R0</code> through <code>R31</code>, floating point registers are <code>F0</code> through <code>F31</code>. </p> <p> <code>R30</code> is reserved to point to <code>g</code>. <code>R23</code> is used as a temporary register. </p>
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Nov 28 19:15:27 UTC 2023 - 36.3K bytes - Viewed (1) -
src/cmd/compile/internal/ssa/_gen/ARM64Ops.go
"R19", "R20", "R21", "R22", "R23", "R24", "R25", "R26", // R27 = REGTMP not used in regalloc "g", // aka R28 "R29", // frame pointer, not used "R30", // aka REGLINK "SP", // aka R31 "F0", "F1", "F2", "F3", "F4", "F5", "F6", "F7", "F8", "F9", "F10", "F11", "F12", "F13", "F14", "F15", "F16", "F17", "F18", "F19", "F20",
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu May 23 15:49:20 UTC 2024 - 58.8K bytes - Viewed (0) -
src/cmd/internal/obj/ppc64/asm9.go
func loadl16(r int, d int64) uint32 { v := uint16(d) if v == 0 { // Avoid generating "ori r,r,0", r != 0. Instead, generate the architectually preferred nop. // For example, "ori r31,r31,0" is a special execution serializing nop on Power10 called "exser". return NOP } return LOP_IRR(OP_ORI, uint32(r), uint32(r), uint32(v)) } // Load the upper 16 bits of a 32b constant into register r.
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed May 15 13:55:28 UTC 2024 - 156.1K bytes - Viewed (0) -
src/runtime/asm_arm64.s
STP (R23, R24), 19*8(RSP) STP (R25, R26), 21*8(RSP) // R27 is temp register. // R28 is g. // R29 is frame pointer (unused). // R30 is LR, which was saved by the prologue. // R31 is SP. CALL runtime·wbBufFlush(SB) LDP 1*8(RSP), (R2, R3) LDP 3*8(RSP), (R4, R5) LDP 5*8(RSP), (R6, R7) LDP 7*8(RSP), (R8, R9) LDP 9*8(RSP), (R10, R11) LDP 11*8(RSP), (R12, R13)
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Sat May 11 20:38:24 UTC 2024 - 43.4K bytes - Viewed (0)