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Results 61 - 70 of 192 for cmpl (0.23 sec)
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src/cmd/compile/internal/ssa/rewriteAMD64.go
b.resetWithControl(BlockAMD64LE, cmp) return true } // match: (If (SETG cmp) yes no) // result: (GT cmp yes no) for b.Controls[0].Op == OpAMD64SETG { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockAMD64GT, cmp) return true } // match: (If (SETGE cmp) yes no) // result: (GE cmp yes no) for b.Controls[0].Op == OpAMD64SETGE {
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Mar 12 19:38:41 UTC 2024 - 712.7K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/armv6.s
LDREXD (R11), R12 // 9fcfbbe1 STREX R3, (R4), R5 // STREX (R4), R3, R5 // 935f84e1 STREXD R8, (R9), g // STREXD (R9), R8, g // 98afa9e1 CMPF F8, F9 // c89ab4ee10faf1ee CMPD.CS F4, F5 // c45bb42e10faf12e CMPF.VS F7 // c07ab56e10faf16e CMPD F6 // c06bb5ee10faf1ee MOVW R4, F8 // 104b08ee MOVW F4, R8 // 108b14ee
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu Dec 21 16:30:51 UTC 2017 - 4.6K bytes - Viewed (0) -
src/cmd/internal/obj/arm/anames.go
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed Oct 16 15:58:33 UTC 2019 - 1.4K bytes - Viewed (0) -
tensorflow/compiler/mlir/tf2xla/tests/legalize-tf.mlir
// CHECK-DAG: [[CMP3:%.+]] = chlo.broadcast_compare %arg1, [[ZEROS2]] {comparison_direction = #chlo<comparison_direction LT>} // CHECK-DAG: [[CMP4:%.+]] = chlo.broadcast_compare [[CMP2]], [[CMP3]] {broadcast_dimensions = array<i64: 1>, comparison_direction = #chlo<comparison_direction NE>} // CHECK-DAG: [[AND:%.+]] = chlo.broadcast_and [[CMP1]], [[CMP4]] // CHECK-DAG: [[ONES:%.+]] = mhlo.constant dense<1>
Registered: Sun Jun 16 05:45:23 UTC 2024 - Last Modified: Mon May 06 18:46:23 UTC 2024 - 335.5K bytes - Viewed (0) -
src/cmd/vendor/golang.org/x/arch/arm/armasm/plan9x.go
{VSQRT_EQ_F32, []int{1, 0}, "VSQRT", "SQRTF"}, {VSQRT_EQ_F64, []int{1, 0}, "VSQRT", "SQRTD"}, {VCMP_EQ_F32, []int{1, 0}, "VCMP", "CMPF"}, {VCMP_EQ_F64, []int{1, 0}, "VCMP", "CMPD"}, {VCMP_E_EQ_F32, []int{1, 0}, "VCMP.E", "CMPF"}, {VCMP_E_EQ_F64, []int{1, 0}, "VCMP.E", "CMPD"}, {VLDR_EQ, []int{1}, "VLDR", "MOV"}, {VSTR_EQ, []int{1}, "VSTR", "MOV"}, {VMOV_EQ_F32, []int{1, 0}, "VMOV", "MOVF"},
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu Oct 19 23:33:33 UTC 2023 - 11.9K bytes - Viewed (0) -
src/cmd/vendor/golang.org/x/arch/ppc64/ppc64asm/plan9.go
LFDUX: "FMOVDU", STFDUX: "FMOVDU", LFSX: "FMOVS", STFSX: "FMOVS", LFSU: "FMOVSU", STFSU: "FMOVSU", LFSUX: "FMOVSU", STFSUX: "FMOVSU", CMPD: "CMP", CMPDI: "CMP", CMPW: "CMPW", CMPWI: "CMPW", CMPLD: "CMPU", CMPLDI: "CMPU", CMPLW: "CMPWU", CMPLWI: "CMPWU", MTSPR: "MOVD", MFSPR: "MOVD", // the width is ambiguous for SPRs B: "BR", BL: "CALL",
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Nov 22 17:16:14 UTC 2022 - 10.9K bytes - Viewed (0) -
test/cmp6.go
Robert Griesemer <******@****.***> 1606801129 -0800
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Dec 01 21:49:31 UTC 2020 - 2.2K bytes - Viewed (0) -
src/html/template/testdata/file1.tmpl
Russ Cox <******@****.***> 1594052821 -0400
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Jul 14 16:54:25 UTC 2020 - 57 bytes - Viewed (0) -
src/html/template/testdata/tmpl2.tmpl
Russ Cox <******@****.***> 1594052821 -0400
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Jul 14 16:54:25 UTC 2020 - 50 bytes - Viewed (0) -
test/cmp.go
Aaron Jacobs <******@****.***> 1435103412 +1000
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Jun 26 03:38:21 UTC 2015 - 7.6K bytes - Viewed (0)