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Results 11 - 20 of 62 for regoff (0.11 sec)

  1. src/cmd/internal/obj/s390x/a.out.go

    	REG_R5
    	REG_R6
    	REG_R7
    	REG_R8
    	REG_R9
    	REG_R10
    	REG_R11
    	REG_R12
    	REG_R13
    	REG_R14
    	REG_R15
    
    	// Floating point registers (FPRs).
    	REG_F0
    	REG_F1
    	REG_F2
    	REG_F3
    	REG_F4
    	REG_F5
    	REG_F6
    	REG_F7
    	REG_F8
    	REG_F9
    	REG_F10
    	REG_F11
    	REG_F12
    	REG_F13
    	REG_F14
    	REG_F15
    
    	// Vector registers (VRs) - only available when the vector
    	// facility is installed.
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Tue Sep 05 16:41:03 UTC 2023
    - 12.4K bytes
    - Viewed (0)
  2. src/cmd/internal/obj/riscv/cpu.go

    	REG_X21
    	REG_X22
    	REG_X23
    	REG_X24
    	REG_X25
    	REG_X26
    	REG_X27
    	REG_X28
    	REG_X29
    	REG_X30
    	REG_X31
    
    	// FP register numberings.
    	REG_F0
    	REG_F1
    	REG_F2
    	REG_F3
    	REG_F4
    	REG_F5
    	REG_F6
    	REG_F7
    	REG_F8
    	REG_F9
    	REG_F10
    	REG_F11
    	REG_F12
    	REG_F13
    	REG_F14
    	REG_F15
    	REG_F16
    	REG_F17
    	REG_F18
    	REG_F19
    	REG_F20
    	REG_F21
    	REG_F22
    	REG_F23
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Wed Mar 20 14:19:33 UTC 2024
    - 13.1K bytes
    - Viewed (0)
  3. src/cmd/internal/obj/ppc64/a.out.go

    	REG_CR7SO
    
    	/* Align FPR and VSR vectors such that when masked with 0x3F they produce
    	   an equivalent VSX register. */
    	/* F0=4160 ... F31=4191 */
    	REG_F0
    	REG_F1
    	REG_F2
    	REG_F3
    	REG_F4
    	REG_F5
    	REG_F6
    	REG_F7
    	REG_F8
    	REG_F9
    	REG_F10
    	REG_F11
    	REG_F12
    	REG_F13
    	REG_F14
    	REG_F15
    	REG_F16
    	REG_F17
    	REG_F18
    	REG_F19
    	REG_F20
    	REG_F21
    	REG_F22
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Mon Apr 01 18:50:29 UTC 2024
    - 16K bytes
    - Viewed (0)
  4. src/cmd/internal/obj/arm64/a.out.go

    	REG_R20
    	REG_R21
    	REG_R22
    	REG_R23
    	REG_R24
    	REG_R25
    	REG_R26
    	REG_R27
    	REG_R28
    	REG_R29
    	REG_R30
    	REG_R31
    
    	// scalar floating point
    	REG_F0
    	REG_F1
    	REG_F2
    	REG_F3
    	REG_F4
    	REG_F5
    	REG_F6
    	REG_F7
    	REG_F8
    	REG_F9
    	REG_F10
    	REG_F11
    	REG_F12
    	REG_F13
    	REG_F14
    	REG_F15
    	REG_F16
    	REG_F17
    	REG_F18
    	REG_F19
    	REG_F20
    	REG_F21
    	REG_F22
    	REG_F23
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Wed Oct 18 17:56:30 UTC 2023
    - 18.1K bytes
    - Viewed (0)
  5. src/vendor/golang.org/x/net/dns/dnsmessage/message.go

    }
    
    func (h *header) unpack(msg []byte, off int) (int, error) {
    	newOff := off
    	var err error
    	if h.id, newOff, err = unpackUint16(msg, newOff); err != nil {
    		return off, &nestedError{"id", err}
    	}
    	if h.bits, newOff, err = unpackUint16(msg, newOff); err != nil {
    		return off, &nestedError{"bits", err}
    	}
    	if h.questions, newOff, err = unpackUint16(msg, newOff); err != nil {
    		return off, &nestedError{"questions", err}
    	}
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Sat Mar 09 00:09:40 UTC 2024
    - 69K bytes
    - Viewed (0)
  6. src/cmd/link/internal/ld/elf.go

    			sh = elfshname(".note.netbsd.ident")
    			resoff -= int64(elfnetbsdsig(sh, uint64(startva), uint64(resoff)))
    
    		case objabi.Hopenbsd:
    			sh = elfshname(".note.openbsd.ident")
    			resoff -= int64(elfopenbsdsig(sh, uint64(startva), uint64(resoff)))
    
    		case objabi.Hfreebsd:
    			sh = elfshname(".note.tag")
    			resoff -= int64(elffreebsdsig(sh, uint64(startva), uint64(resoff)))
    		}
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Mon Apr 22 13:29:54 UTC 2024
    - 63.6K bytes
    - Viewed (0)
  7. src/cmd/internal/obj/wasm/wasmobj.go

    	"R10": REG_R10,
    	"R11": REG_R11,
    	"R12": REG_R12,
    	"R13": REG_R13,
    	"R14": REG_R14,
    	"R15": REG_R15,
    
    	"F0":  REG_F0,
    	"F1":  REG_F1,
    	"F2":  REG_F2,
    	"F3":  REG_F3,
    	"F4":  REG_F4,
    	"F5":  REG_F5,
    	"F6":  REG_F6,
    	"F7":  REG_F7,
    	"F8":  REG_F8,
    	"F9":  REG_F9,
    	"F10": REG_F10,
    	"F11": REG_F11,
    	"F12": REG_F12,
    	"F13": REG_F13,
    	"F14": REG_F14,
    	"F15": REG_F15,
    
    	"F16": REG_F16,
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Wed Jun 14 00:03:57 UTC 2023
    - 34.6K bytes
    - Viewed (0)
  8. src/internal/coverage/slicereader/slicereader.go

    		}
    		r.off = offset
    		return offset, nil
    	case io.SeekCurrent:
    		newoff := r.off + offset
    		if newoff < 0 || newoff > int64(len(r.b)) {
    			return 0, fmt.Errorf("invalid seek: new offset %d (out of range [0 %d]", newoff, len(r.b))
    		}
    		r.off = newoff
    		return r.off, nil
    	case io.SeekEnd:
    		newoff := int64(len(r.b)) + offset
    		if newoff < 0 || newoff > int64(len(r.b)) {
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Tue May 23 11:36:28 UTC 2023
    - 2.5K bytes
    - Viewed (0)
  9. src/internal/coverage/slicewriter/slicewriter.go

    		return offset, nil
    	case io.SeekCurrent:
    		newoff := sws.off + offset
    		if newoff != sws.off && (newoff < 0 || newoff > int64(len(sws.payload))) {
    			return 0, fmt.Errorf("invalid seek: new offset %d (out of range [0 %d]", newoff, len(sws.payload))
    		}
    		sws.off += offset
    		return sws.off, nil
    	case io.SeekEnd:
    		newoff := int64(len(sws.payload)) + offset
    		if newoff != sws.off && (newoff < 0 || newoff > int64(len(sws.payload))) {
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Wed Apr 26 12:44:26 UTC 2023
    - 2.5K bytes
    - Viewed (0)
  10. src/cmd/internal/obj/ppc64/asm_test.go

    	}
    	var testType = []struct {
    		rstart int
    		rend   int
    		msk    int
    		rout   int
    	}{
    		{REG_VS0, REG_VS63, 63, 0},
    		{REG_R0, REG_R31, 31, 0},
    		{REG_F0, REG_F31, 31, 0},
    		{REG_V0, REG_V31, 31, 0},
    		{REG_V0, REG_V31, 63, 32},
    		{REG_F0, REG_F31, 63, 0},
    		{REG_SPR0, REG_SPR0 + 1023, 1023, 0},
    		{REG_CR0, REG_CR7, 7, 0},
    		{REG_CR0LT, REG_CR7SO, 31, 0},
    	}
    	for _, t := range testType {
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Fri Feb 09 22:14:57 UTC 2024
    - 17.3K bytes
    - Viewed (0)
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