MOVL (AX)(Y0*1), AX             // ERROR "invalid instruction"
	// VSIB/VM is invalid without vector index.
	// TODO(quasilyte): improve error message (#21860).
	// "invalid VSIB address (missing vector index)"
	VPGATHERQQ Y2, (BP), Y1         // ERROR "invalid instruction"
	// AVX2GATHER mask/index/dest #UD cases.
	VPGATHERQQ Y2, (BP)(X2*2), Y2   // ERROR "mask, index, and destination registers should be distinct"

||    conditional OR     p || q  is  "if p then true else q"
!     NOT                !p      is  "not p"
</pre>


<h3 id="Address_operators">Address operators</h3>

<p>
For an operand <code>x</code> of type <code>T</code>, the address operation
<code>&amp;x</code> generates a pointer of type <code>*T</code> to <code>x</code>.
The operand must be <i>addressable</i>,

//
// to sbCheck, and returns true. If a is a simple variable or field reference,
// it writes
//
//	_cgoIndexNN := &a
//
// and dereferences the uses of _cgoIndexNN. Taking the address avoids
// making a copy of an array.
//
// This tells _cgoCheckPointer to check the complete contents of the
// slice or array being indexed, but no other part of the memory allocation.

	JMP	4(X5)					// 67804200

	// CALL and JMP to symbol are encoded as JAL (using LR or ZERO
	// respectively), with a R_RISCV_JAL relocation. The linker resolves
	// the real address and updates the immediate, using a trampoline in
	// the case where the address is not directly reachable.
	CALL	asmtest(SB)				// ef000000
	JMP	asmtest(SB)				// 6f000000

	// Branch pseudo-instructions
	BEQZ	X5, 2(PC)				// 63840200

	FMOVD	0x1006ff8(R1), F2	// FMOVD	16805880(R1), F2	// 3bfc7f9162ff7ffd

// very large or unaligned offset uses constant pool.
// the encoding cannot be checked as the address of the constant pool is unknown.
// here we only test that they can be assembled.
	MOVB	R1, 0x1000000(R2)	// MOVB		R1, 16777216(R2)
	MOVB	R1, 0x44332211(R2)	// MOVB		R1, 1144201745(R2)

		case "UXTH":
			if a.Type == obj.TYPE_MEM {
				return errors.New("invalid shift for the register offset addressing mode")
			}
			a.Reg = arm64.REG_UXTH + Rnum
		case "UXTW":
			// effective address of memory is a base register value and an offset register value.
			if a.Type == obj.TYPE_MEM {
				a.Index = arm64.REG_UXTW + Rnum
			} else {
				a.Reg = arm64.REG_UXTW + Rnum
			}
		case "UXTX":

pkg debug/elf, const DT_GNU_PRELINKED DynTag
pkg debug/elf, const DT_MIPS_AUX_DYNAMIC = 1879048241
pkg debug/elf, const DT_MIPS_AUX_DYNAMIC DynTag
pkg debug/elf, const DT_MIPS_BASE_ADDRESS = 1879048198
pkg debug/elf, const DT_MIPS_BASE_ADDRESS DynTag
pkg debug/elf, const DT_MIPS_COMPACT_SIZE = 1879048239
pkg debug/elf, const DT_MIPS_COMPACT_SIZE DynTag
pkg debug/elf, const DT_MIPS_CONFLICT = 1879048200

pkg syscall (freebsd-arm64), type Iovec struct, Base *uint8
pkg syscall (freebsd-arm64), type Iovec struct, Len uint64
pkg syscall (freebsd-arm64), type IPMreqn struct
pkg syscall (freebsd-arm64), type IPMreqn struct, Address [4]uint8
pkg syscall (freebsd-arm64), type IPMreqn struct, Ifindex int32
pkg syscall (freebsd-arm64), type IPMreqn struct, Multiaddr [4]uint8
pkg syscall (freebsd-arm64), type IPv6MTUInfo struct

pkg syscall (freebsd-riscv64), type ICMPv6Filter struct, Filt [8]uint32 #53466
pkg syscall (freebsd-riscv64), type IPMreqn struct #53466
pkg syscall (freebsd-riscv64), type IPMreqn struct, Address [4]uint8 #53466
pkg syscall (freebsd-riscv64), type IPMreqn struct, Ifindex int32 #53466
pkg syscall (freebsd-riscv64), type IPMreqn struct, Multiaddr [4]uint8 #53466

pkg net/http/cookiejar, type PublicSuffixList interface, String() string
pkg net/http/httptest, const DefaultRemoteAddr = "1.2.3.4"
pkg net/mail, func ParseAddress(string) (*Address, error)
pkg net/mail, func ParseAddressList(string) ([]*Address, error)
pkg net/rpc, const DefaultDebugPath = "/debug/rpc"
pkg net/rpc, const DefaultRPCPath = "/_goRPC_"
pkg net/smtp, method (*Client) Hello(string) error