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Results 11 - 17 of 17 for RegAlloc (0.14 sec)
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src/cmd/compile/internal/ssa/html.go
// Contains phase names which are expanded by default. Other columns are collapsed. let expandedDefault = [ "start", "deadcode", "opt", "lower", "late-deadcode", "regalloc", "genssa", ]; if (history.state === null) { history.pushState({expandedDefault}, "", location.href); } // ordered list of all available highlight colors var highlights = [
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed Oct 04 15:11:40 UTC 2023 - 34.8K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/op.go
} type regInfo struct { // inputs encodes the register restrictions for an instruction's inputs. // Each entry specifies an allowed register set for a particular input. // They are listed in the order in which regalloc should pick a register // from the register set (most constrained first). // Inputs which do not need registers are not listed. inputs []inputInfo // clobbers encodes the set of registers that are overwritten by
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon Apr 22 15:29:10 UTC 2024 - 18.7K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/MIPSOps.go
// H (half word) = 16 bit // HU = 16 bit unsigned // B (byte) = 8 bit // BU = 8 bit unsigned // F (float) = 32 bit float // D (double) = 64 bit float // Note: registers not used in regalloc are not included in this list, // so that regmask stays within int64 // Be careful when hand coding regmasks. var regNamesMIPS = []string{ "R0", // constant 0 "R1", "R2", "R3", "R4", "R5", "R6",
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed May 24 14:43:03 UTC 2023 - 24K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/RISCV64Ops.go
} regNamesRISCV64 = append(regNamesRISCV64, name) regNamed[name] = mask return mask } // General purpose registers. for r := 0; r <= 31; r++ { if r == riscv64REG_LR { // LR is not used by regalloc, so we skip it to leave // room for pseudo-register SB. continue } mask := addreg(r, "") // Add general purpose registers to gpMask. switch r {
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu Mar 07 14:57:07 UTC 2024 - 30.7K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/func.go
dumpFileSeq uint8 // the sequence numbers of dump file. (%s_%02d__%s.dump", funcname, dumpFileSeq, phaseName) IsPgoHot bool // when register allocation is done, maps value ids to locations RegAlloc []Location // temporary registers allocated to rare instructions tempRegs map[ID]*Register // map from LocalSlot to set of Values that we want to store in that slot. NamedValues map[LocalSlot][]*Value
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon Jun 10 19:44:43 UTC 2024 - 25.8K bytes - Viewed (0) -
src/cmd/compile/internal/test/testdata/arith_test.go
} } //go:noinline func test64BitConstAdd_ssa(a, b int64) int64 { return a + 575815584948629622 + b + 2991856197886747025 } // testRegallocCVSpill tests that regalloc spills a value whose last use is the // current value. func testRegallocCVSpill(t *testing.T) { want := int8(-9) if got := testRegallocCVSpill_ssa(1, 2, 3, 4); want != got {
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Dec 01 19:30:59 UTC 2023 - 43.5K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/genericOps.go
// (particularly stack maps). It takes a memory arg so it // gets correctly ordered with respect to GC safepoints. // It gets compiled to nothing, so its result must in the same // register as its argument. regalloc knows it can use any // allocatable integer register for OpConvert. // arg0=ptr/int arg1=mem, output=int/ptr {name: "Convert", argLength: 2, zeroWidth: true, resultInArg0: true},
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu May 23 15:49:20 UTC 2024 - 42.6K bytes - Viewed (0)